公开(公告)号：EP0963021A4

公开(公告)日：2001-01-24

申请号：EP98957178

申请日：1998-12-04

Applicant: FURUKAWA ELECTRIC CO LTD

Inventor： MIYAJIMA KAZUO ,  HASEGAWA SHIN ,  SAWAKI YOSHIAKI

IPC: H02G3/08 ,  H02G3/16 ,  H02G5/00 ,  H05K3/20 ,  H05K3/32 ,  H05K7/06 ,  H01R9/22 ,  H01R43/16

CPC classification number: H02G3/16 ,  H02G3/081 ,  H02G5/005 ,  H05K3/202 ,  H05K3/326 ,  H05K2201/091 ,  H05K2201/10946 ,  H05K2201/2072 ,  Y10S439/949 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49128 ,  Y10T29/49151 ,  Y10T29/49153 ,  Y10T29/49833 ,  Y10T29/49845 ,  Y10T29/49908

Abstract: A bus bar wiring board comprising a bus bar pattern for electric wiring formed in a predetermined shape, and a bus bar piece formed separately from the bus bar pattern and electrically connected and secured to the bus bar pattern. A method of producing the bus bar wiring board comprising a bus bar pattern punching step for punching a bus bar pattern for electric wiring that is laid out in a predetermined shape out of an electrically conducting metal plate, a bus bar piece punching step for punching a bus bar piece laid out in a predetermined shape in a remaining space on the electrically conducting metal plate, and a connection step for electrically connecting and securing together the bus bar pattern punched in the bus bar pattern punching step and the bus bar pieve punched in the bus bar piece punching step, whereby reducing the waste in the electrically conducting metal plate out of which the bus bar patterns are punched and decreasing the cost of production or the cost of a product.

Abstract translation: 一种汇流条布线板，包括形成为预定形状的电线的母线图形，以及与母线图案分开形成的母线条，并且电连接并固定到母线图案。 一种母线布线板的制造方法，其特征在于，包括：母线条冲孔工序，用于冲压导电金属板中以规定形状布置的电气布线的母线图形;冲压步骤 在导电金属板上的剩余空间中以预定形状布置的母线条，以及连接步骤，用于将冲压在母线图案冲压步骤中的母线图形和将冲压在母线条冲压步骤中的母线棒电连接并固定在一起 母线冲压步骤，从而减少导电金属板中的浪费，其中冲压母线图案并降低生产成本或产品成本。

公开(公告)号：EP0963021A1

公开(公告)日：1999-12-08

申请号：EP98957178.1

申请日：1998-12-04

Applicant: The Furukawa Electric Co., Ltd.

Inventor： MIYAJIMA, Kazuo ,  HASEGAWA, Shin ,  SAWAKI, Yoshiaki

IPC: H02G3/16

CPC classification number: H02G3/16 ,  H02G3/081 ,  H02G5/005 ,  H05K3/202 ,  H05K3/326 ,  H05K2201/091 ,  H05K2201/10946 ,  H05K2201/2072 ,  Y10S439/949 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49128 ,  Y10T29/49151 ,  Y10T29/49153 ,  Y10T29/49833 ,  Y10T29/49845 ,  Y10T29/49908

Abstract: A bus bar wiring board comprising a bus bar pattern for electric wiring formed in a predetermined shape, and a bus bar piece formed separately from the bus bar pattern and electrically connected and secured to the bus bar pattern. A method of producing the bus bar wiring board comprising a bus bar pattern punching step for punching a bus bar pattern for electric wiring that is laid out in a predetermined shape out of an electrically conducting metal plate, a bus bar piece punching step for punching a bus bar piece laid out in a predetermined shape in a remaining space on the electrically conducting metal plate, and a connection step for electrically connecting and securing together the bus bar pattern punched in the bus bar pattern punching step and the bus bar pieve punched in the bus bar piece punching step, whereby reducing the waste in the electrically conducting metal plate out of which the bus bar patterns are punched and decreasing the cost of production or the cost of a product.

公开(公告)号：EP0800754A4

公开(公告)日：1999-06-09

申请号：EP95933164

申请日：1995-09-20

Applicant: TESSERA INC

Inventor： KOVAC ZLATA ,  MITCHELL CRAIG S ,  DISTEFANO THOMAS H

IPC: H01L23/12 ,  H01L21/56 ,  H01L21/60 ,  H01L23/28 ,  H01L23/48 ,  H01L23/498 ,  H05K1/11 ,  H05K3/36 ,  H05K3/40 ,  H05K1/02 ,  H01R4/58 ,  H01R9/09 ,  H05K3/30

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/72 ,  H01L24/75 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/81801 ,  H01L2224/83136 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/118 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49174 ,  H01L2924/00014

Abstract: A method and an apparatus for providing a planar and compliant interface between a semiconductor chip (120) and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The compliant interface is comprised of a plurality of compliant pads (110) defining channels (117) between adjacent pads. The pads are typically compressed between a flexible film chip carrier (100) and the chip. A compliant filler (170) is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.

公开(公告)号：EP0870325A4

公开(公告)日：1998-10-14

申请号：EP95924747

申请日：1995-06-29

IPC: H01L21/60 ,  H01L21/30 ,  H01L21/48 ,  H01L21/603 ,  H01L23/12 ,  H01L23/22 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64 ,  H01R12/71 ,  H05K1/11 ,  H05K3/36 ,  H05K3/40

CPC classification number: H01L23/4985 ,  H01L21/4839 ,  H01L23/22 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/642 ,  H01L24/72 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01066 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/118 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49158 ,  H01L2924/00 ,  H01L2224/48

Abstract: A microelectronic connection component includes a dielectric sheet (34) having an area array of elongated, strip-like leads (60). Each lead has a terminal end (66) fastened to the sheet and a tip end (68) detachable from the sheet. Each lead extends horizontally parallel to the sheet, from its terminal end to its tip end. The tip ends are attached to a second element, such as another dielectric sheet or a semiconductor wafer (86). The first and second elements are then moved relative to one another to advance the tip end of each lead vertically away from the dielectric sheet and deform the leads into a bent, vertically extensive configuration. The preferred structures provide semiconductor chip assemblies with a planar area array of contacts on the chip, an array of terminals on the sheet positioned so that each terminal is substantially over the corresponding contact, and an array of metal S-shaped ribbons connected between the terminals and contacts. A compliant dielectric material may be provided between the sheet and chip, substantially surrounding the S-shaped ribbons.

Abstract translation: 微电子连接部件包括具有细长条状引线（60）的区域阵列的电介质片（34）。 每根引线具有一个固定在薄片上的终端（66）和一个可从薄片上拆下的尖端（68）。 每条引线从其末端到末端水平延伸，平行于片材。 末端连接到第二元件，例如另一电介质片或半导体晶片（86）。 然后使第一和第二元件相对于彼此移动，以使每个引线的末端垂直远离电介质片并使引线变形为弯曲的竖直延伸结构。 优选的结构为半导体芯片组件提供芯片上的触点的平面区域阵列，片上的端子阵列被定位成使得每个端子基本上位于相应的触点上方，并且连接在端子之间的金属S形带的阵列 和联系人。 可以在片和芯片之间提供柔性介电材料，基本上围绕S形带。

公开(公告)号：EP0870325A1

公开(公告)日：1998-10-14

申请号：EP95924747.0

申请日：1995-06-29

Applicant: TESSERA, INC.

Inventor： DISTEFANO, Thomas, H. ,  SMITH, John, W.

IPC: H01L21 ,  H01L23 ,  H01R12 ,  H05K3 ,  H05K1

CPC classification number: H01L23/4985 ,  H01L21/4839 ,  H01L23/22 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/642 ,  H01L24/72 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01066 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/118 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49158 ,  H01L2924/00 ,  H01L2224/48

Abstract: A microelectronic connection component includes a dielectric sheet (34) having an area array of elongated, strip-like leads (60). Each lead has a terminal end (66) fastened to the sheet and a tip end (68) detachable from the sheet. Each lead extends horizontally parallel to the sheet, from its terminal end to its tip end. The tip ends are attached to a second element, such as another dielectric sheet or a semiconductor wafer (86). The first and second elements are then moved relative to one another to advance the tip end of each lead vertically away from the dielectric sheet and deform the leads into a bent, vertically extensive configuration. The preferred structures provide semiconductor chip assemblies with a planar area array of contacts on the chip, an array of terminals on the sheet positioned so that each terminal is substantially over the corresponding contact, and an array of metal S-shaped ribbons connected between the terminals and contacts. A compliant dielectric material may be provided between the sheet and chip, substantially surrounding the S-shaped ribbons.

公开(公告)号：EP0800754A1

公开(公告)日：1997-10-15

申请号：EP95933164.0

申请日：1995-09-20

Applicant: TESSERA, INC.

Inventor： KOVAC, Zlata ,  MITCHELL, Craig ,  DISTEFANO, Thomas

IPC: H01L23 ,  H01L21 ,  H05K3 ,  H05K1

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/72 ,  H01L24/75 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/81801 ,  H01L2224/83136 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/118 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49174 ,  H01L2924/00014

Abstract: A method and an apparatus for providing a planar and compliant interface between a semiconductor chip (120) and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The compliant interface is comprised of a plurality of compliant pads (110) defining channels (117) between adjacent pads. The pads are typically compressed between a flexible film chip carrier (100) and the chip. A compliant filler (170) is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.

公开(公告)号：EP0286422B1

公开(公告)日：1994-06-15

申请号：EP88303151.0

申请日：1988-04-08

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Yamamoto, Nobumasa Du Pont Japan Ltd.

IPC: H01R9/07

CPC classification number: H01R12/68 ,  H05K1/118 ,  H05K3/306 ,  H05K3/326 ,  H05K2201/091 ,  H05K2201/1034 ,  H05K2201/1059 ,  H05K2203/1189

公开(公告)号：EP0540104A1

公开(公告)日：1993-05-05

申请号：EP92203269.3

申请日：1992-10-23

Applicant: Philips Electronics N.V. ,  HÜLS TROISDORF AG

Inventor： Bruckner, Helmut ,  Köpnick, Siegfried ,  Uggowitzer, Werner

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/4084 ,  H05K3/3447 ,  H05K3/3452 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4652 ,  H05K3/4676 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/091 ,  H05K2203/063 ,  Y10T29/49155 ,  Y10T156/109 ,  Y10T156/1092 ,  Y10T156/1093

Abstract: A two-layer or multilayer printed circuit board (1) comprises a support plate (2) which consists of a basic material and which carries a first conductor pattern (3) and a second conductor pattern (17) connected to the support plate (2) via an adhesive layer (11) consisting of an electrically insulating adhesive material. At least one opening (12, 13) is provided in the adhesive layer (11), which opening leads to a connecting section (4, 5) of the first conductor pattern (3) and to which a connecting section (18, 19) of the second conductor pattern (17) extends, and by means of which the connecting sections (4, 5, 18, 19) of the two conductor patterns (3, 17) can be electrically interconnected by means of an electrically conducting material connection (28, 29). The adhesive layer (11) here consists of an adhesive material which in a certain temperature range has a higher hardness than the region (2a) of the support plate (2) adjoining the first conductor pattern (3), and the first conductor pattern (3) is pressed into the support plate (2) by the adhesive layer (11) exclusively in its region covered by the adhesive layer (11) as a result of a pressing process for joining together the adhesive layer (11) and the support plate (2), while the region of each connecting section (4, 5) of the first conductor pattern (3) surrounded by an opening (12, 13) is given a curved shape in the direction of a connecting section (18, 19) of the second conductor pattern (17).

Abstract translation: 的双层或多层印刷电路板（1）包括支承板（2）其中besteht碱性材料制成并带有一个第一导体图案（3）和连接到所述支撑板的第二导体图案（17）（2 ）通过由电绝缘性粘接材料的粘合层（11）上。 至少一个开口（12,13）设置在所述粘合剂层提供（11），该开口通向连接部（4,5）的第一导体图案的（3）和到其上连接部（18，19） 第二导体图案（17）延伸，并且借助于该两个导体图案的连接部（4，5，18，19）（3,17）能够电通过导电材料连接的手段（互连 28，29）。 其在一定温度范围内具有较高的硬度比支撑板（2）邻接的所述第一导体图案（3），并且所述第一导体图案的区域（2a）中的粘合材料的粘合层（11）这里besteht（ 3）被压入支承板（2）通过粘接层（11）独家中）通过粘合层（11）作为用于连接在一起的粘接层（11按压处理的结果覆盖其区域和所述支撑板 （2），而每个连接部分的区域（4,5）（3）通过在开口（12,13）在连接部（18，19）的方向上给定的弯曲形状所包围的第一导体图案的 的第二导体图案（17）。

公开(公告)号：EP0380342A3

公开(公告)日：1990-10-24

申请号：EP90300798.7

申请日：1990-01-25

Applicant: STAG MICROSYSTEMS LTD.

Inventor： Gilbert, Ian David ,  Piggott, Bruce Reginald ,  Humphreys, Chris

IPC: G01R1/073 ,  G01R1/067

CPC classification number: H05K3/326 ,  G01R1/0416 ,  G01R1/0433 ,  G01R1/0735 ,  H05K1/182 ,  H05K1/189 ,  H05K2201/091 ,  H05K2201/1059 ,  H05K2201/10689 ,  H05K2203/0165

Abstract: An electrical contact comprises a printed circuit layout defining the contact elements on a flexible membrane (6). The membrane is attached to a resilient foam backing (10). The backing urges the contacts into engagement with the terminals of a component to which connection is to be made and also accommodates for differences in the location of the terminals from one component to another. The invention provides reliable electrical connection both in temporary (i.e. programmed test) situations and more permanent applications.

Abstract translation: 电触点包括限定柔性膜（6）上的接触元件的印刷电路布局。 膜连接到弹性泡沫背衬（10）。 背衬促使触点与要连接的部件的端子接合，并且还适应端子从一个部件到另一个部件的位置的差异。 本发明在临时（即编程的测试）情况和更永久的应用中提供可靠的电连接。

公开(公告)号：EP0303485A3

公开(公告)日：1989-11-08

申请号：EP88307441.1

申请日：1988-08-11

Applicant: BICC Public Limited Company

Inventor： Lawrence, Howard

IPC: H05K3/32 ,  H05K1/00 ,  H05K3/40

CPC classification number: H05K3/4046 ,  H05K1/118 ,  H05K3/0064 ,  H05K3/306 ,  H05K3/326 ,  H05K3/4611 ,  H05K2201/091 ,  H05K2201/09609 ,  H05K2201/10303 ,  H05K2201/1059 ,  H05K2201/2009

Abstract: A circuit board in which the patterns of electrically conductive strips and/or pads can be of either standard or non-standard form and which can be designed and assembled by a user comprises a rigid electrically insulating board 1 having a multiplicity of holes 2 through the board arranged in a pattern of rows and columns and, secured to one major surface of the board, a separately formed flexible sheet 4 of electrically insulating material carrying on the surface of the sheet remote from the board a pattern of electrically conductive strips and/or pads 8 which overlies holes in the board. The strips and/or pads 8 are of such an electrically conductive material and of such a thickness that, when a pin C is urged through an electrically conductive strip or pad and the underlying flexible sheet 4 into an underlying hole 2 in the board, electrically conductive material pierced by the pin will effect an electrical contact with the pin passing through the material.

Abstract translation: 导电条和/或焊盘的图案可以是标准形式或非标准形式并且可由用户设计和组装的电路板包括刚性电绝缘板1，其具有多个孔2穿过 板被布置成行和列的图案，并且固定到板的一个主表面，分开形成的电绝缘材料的柔性片4，其在片材的远离板的表面上承载导电条的图案和/或 垫板8覆盖板上的孔。 条和/或焊盘8具有这样的导电材料，并且具有这样的厚度，使得当销C被推动穿过导电条或焊盘并且下面的柔性片4进入板中的下面的孔2时，电 由引脚刺穿的导电材料将影响与引脚穿过材料的电接触。