公开(公告)号：EP2265101A1

公开(公告)日：2010-12-22

申请号：EP10172106.6

申请日：2000-09-01

Applicant: IBIDEN CO., LTD.

Inventor： Inagaki, Yasushi ,  Asai, Motoo ,  Wang, Dongdong ,  Yabashi, Hideo ,  Shirai, Seiji

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 is constituted by providing a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

Abstract translation: 片状电容器20设置在印刷电路板10的芯基板30中。这使得可以缩短IC芯片90和芯片电容器20之间的距离并减小环路电感。 由于通过以多层方式设置第一树脂基板30a，第二树脂基板30b和第三树脂基板30c来构成芯基板30，所以能够获得足够的强度。

公开(公告)号：EP2194766A1

公开(公告)日：2010-06-09

申请号：EP08792271.2

申请日：2008-07-31

Applicant: Soshin Electric Co. Ltd. ,  NGK Insulators, Ltd.

Inventor： HASEGAWA, Tomoyuki ,  NAGATOMO, Takashi ,  IDE, Yoshinori ,  OTAGIRI, Tadashi

IPC: H05K3/46 ,  C04B35/46 ,  H01B3/12 ,  H05K1/03

CPC classification number: H05K1/162 ,  B32B18/00 ,  C04B35/46 ,  C04B35/462 ,  C04B35/468 ,  C04B35/4682 ,  C04B35/62675 ,  C04B2235/3215 ,  C04B2235/3281 ,  C04B2235/3284 ,  C04B2235/3298 ,  C04B2235/365 ,  C04B2235/6025 ,  C04B2235/656 ,  C04B2235/96 ,  C04B2237/341 ,  C04B2237/346 ,  H01B3/12 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/165 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10674 ,  Y10T428/24926

Abstract: It is provided a ceramic multilayer substrate obtained by co-sintering a low dielectric constant layer made of an insulating material of a low dielectric constant and a high dielectric constant layer of a dielectric material of a high dielectric constant. The low dielectric constant layer includes a ceramic component of xBaO-yTiO 2 -zZnO ("x", "y" and "z" represent molar ratios, respectively, and satisfy the relationship: x+y+z= 1; 0.09 ≦ x ≦ 0.20; 0.49 ≦ y ≦ 0.61; 0.19 ≦ z ≦ 0.42) and 1.0 to 5.0 weight parts of a glass component comprising boron oxide with respect to 100 weight parts of the ceramic component. The high dielectric layer is made of a barium titanate based dielectric material with CuO and Bi 2 O 3 added thereto.

Abstract translation: 提供了一种陶瓷多层基板，其通过共烧烧由低介电常数的绝缘材料制成的低介电常数层和具有高介电常数的介电材料的高介电常数层而获得。 低介电常数层包括xBaO-yTiO 2 -zZnO的陶瓷成分（“x”，“y”和“z”分别表示摩尔比，满足关系：x + y + z = 1; 0.09‰| 相对于100重量份的陶瓷成分，含有氧化硼的玻璃成分为1.0〜5.0重量份，x‰| 0.20; 0.49‰| y‰| 0.61; 0.19‰| z‰| 0.42） 高介电层由添加有CuO和Bi 2 O 3的钛酸钡基电介质材料制成。

公开(公告)号：EP1062849B1

公开(公告)日：2010-03-03

申请号：EP99964046.9

申请日：1999-12-02

Applicant: MOTOROLA, INC.

Inventor： DUNN, Gregory, J. ,  LACH, Larry ,  SAVIC, Jovica ,  BEUHLER, Allyson ,  SIMONS, Everett

IPC: H05K1/16 ,  H05K1/00 ,  H05K3/00

CPC classification number: H05K3/0082 ,  H01F17/0013 ,  H01F41/041 ,  H01F41/046 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2203/0551

Abstract: A method for fabricating circuit board conductors (24A & 24B) generally entails forming a metal layer (24) on a positive-acting photodielectric layer (22), and etching the metal layer to form at least two conductor traces (24A & 24B) that cover separate regions of the photodielectric layer while exposing a third region therebetween. The third region of the photodielectric layer is developed using the two traces as a photomask and removed. Thus, the traces are not only separated by a void (30) formed when the metal layer was etched, but are also separated by the opening (32) formed in the photodielectric layer by the removal of the third region of the photodielectric layer. A ferrite-filled polymer may also be deposited in the void and opening to form a ferrite core (34). Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.

公开(公告)号：EP2015623A4

公开(公告)日：2009-12-16

申请号：EP07742023

申请日：2007-04-20

Applicant: IBIDEN CO LTD

Inventor： KARIYA TAKASHI ,  FURUTANI TOSHIKI ,  KAWANISHI TAKESHI

IPC: H05K3/46

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2224/05599

公开(公告)号：EP2102268A2

公开(公告)日：2009-09-23

申请号：EP07862749.4

申请日：2007-12-11

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： SUMMERS, John D.

IPC: C08G73/00 ,  C08G73/10 ,  C08L79/00 ,  C08L79/08 ,  C09D179/08 ,  C08K5/00 ,  H01G4/00 ,  H05K1/00

CPC classification number: H05K1/162 ,  C08L79/08 ,  C09D179/08 ,  H05K3/1291 ,  H05K2201/0154 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126

Abstract: This invention relates to compositions, and the use of such compositions for protective coatings, particularly of electronic devices. The invention concerns fired-on-foil ceramic capacitors coated with a composite encapsulant and embedded in a printed wiring board.

公开(公告)号：EP2092807A2

公开(公告)日：2009-08-26

申请号：EP07862748.6

申请日：2007-12-11

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： SUMMERS, John D. ,  MUTOH, Tsutomu

IPC: H05K1/16 ,  H01G4/224

CPC classification number: H05K1/162 ,  H01G4/224 ,  H01L23/50 ,  H01L2924/0002 ,  H05K3/1291 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126 ,  H01L2924/00

Abstract: This invention relates to compositions, and the use of such compositions for protective coatings, particularly of electronic devices. The invention concerns a f ired-on-foil ceramic capacitors coated with a two-layer composite encapsulant and embedded in a printed wiring board. The two-layer encapsulant comprises a first layer comprising a polyimide and a second layer comprising an epoxy-containing cyclic olefin resin, a phenolic resin and an epoxy catalyst.

Abstract translation: 本发明涉及组合物，以及这种组合物用于保护涂层，特别是电子器件的用途。 本发明涉及一种涂覆有双层复合密封剂并嵌入印刷线路板中的箔上陶瓷电容器。 双层密封剂包含含聚酰亚胺的第一层和含环氧树脂的环烯烃树脂，酚醛树脂和环氧树脂催化剂的第二层。

公开(公告)号：EP2081419A2

公开(公告)日：2009-07-22

申请号：EP09156903.8

申请日：2000-09-01

Applicant: Ibiden Co., Ltd.

Inventor： Inagaki, Yasushi c/o Ogaki-kita-kojou, Ibiden Co., Ltd. ,  Asai, Motoo c/o Ogaki-kita-kojou Ibiden Co., Ltd. ,  Wang, Dongdong c/o Ogaki-kita-kojou, Ibiden Co., Ltd., ,  Yabashi, Hideo c/o Ogaki-kita-kojou Ibiden Co., Ltd., ,  Shirai, Seiji c/o Ogaki-kita-kojou, Ibiden Co., Ltd.,

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 is constituted by providing a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

Abstract translation: 芯片电容器（20）设置在印刷电路板（10）的芯基板（30）中。 这使得可以缩短IC芯片（90）和芯片电容器（20）之间的距离并减小环路电感。 由于通过以多层方式设置第一树脂基板（30a），第二树脂基板（30b）和第三树脂基板（30c）构成芯基板（30），所以芯基板（30）能够获得足够的强度。

公开(公告)号：EP2077703A1

公开(公告)日：2009-07-08

申请号：EP09156862.6

申请日：2000-09-01

Applicant: IBIDEN CO., LTD.

Inventor： Inagaki, Yasushi ,  Asai, Motoo ,  Wang, Dongdong ,  Yabashi, Hideo ,  Shirai, Seiji

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 is constituted by providing a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

公开(公告)号：EP2034810A1

公开(公告)日：2009-03-11

申请号：EP06822140.7

申请日：2006-10-24

Applicant: IBIDEN CO., LTD.

Inventor： TAKAHASHI, Michimasa ,  AOYAMA, Masakazu

IPC: H05K3/46

CPC classification number: H05K3/4644 ,  H05K3/0035 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4691 ,  H05K2201/0187 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627

Abstract: A flexible substrate 13 having conductor patterns 132 and 133, and a non-flexible substrate 111 with rigidity are disposed adjacent to each other in the horizontal direction. The flexible substrate 13 and the non-flexible substrate 111 are covered with insulating layers 111 and 113 so that at least a portion of the flexible substrate is exposed. Vias 116 and 141 are formed in the insulating layers 111 and 116 so as to reach the conductor patterns 132 and 133 of the flexible substrate 13, and wirings 117 and 142 are formed by plating to reach the conductor patterns 132 and 133 through the vias 116 and 141. The insulating layers 114, 115, 144, and 145 are laminated on the insulating layers 111 and 113, and circuits 123 and 150 are formed for connection of wiring.

Abstract translation: 具有导体图案132和133的柔性基板13和具有刚性的非柔性基板111在水平方向上彼此相邻布置。 柔性基板13和非柔性基板111被绝缘层111和113覆盖，使得柔性基板的至少一部分露出。 通孔116和141形成在绝缘层111和116中以便到达柔性基板13的导体图案132和133，并且布线117和142通过电镀形成以通过通孔116到达导体图案132和133 绝缘层114,115,144和145层叠在绝缘层111和113上，并且形成电路123和150用于布线的连接。

公开(公告)号：EP1951016A1

公开(公告)日：2008-07-30

申请号：EP06822610.9

申请日：2006-10-30

Applicant: IBIDEN CO., LTD.

Inventor： TAKAHASHI, Michimasa ,  AOYAMA, Masakazu

IPC: H05K3/46

CPC classification number: H05K3/4691 ,  H05K1/0218 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4664 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096

Abstract: A flexible substrate (112) having a conductive pattern (132, 133) and a non-flexible base material (112) having rigidity are disposed adjacent to each other in a horizontal direction. An insulating layer (111, 113) containing an inorganic material (111a, 111b, 113a, 113b) covers the flexible substrate (13) and the non-flexible base material (112) so as to expose at least a part of the flexible substrate (13). A via (116, 141) which reaches the conductive pattern (132, 133) of the flexible substrate (13) is formed in the insulating layer, a wire (117, 118, 142, 143) extending to the conductive pattern (132, 133) is formed through the via (116, 141) by plating. On the insulating layer (111, 113), an upper insulating layer (114, 115, 144, 145) is laminated, and a circuit (123, 150) is formed.

Abstract translation: 具有导电图案（132,133）和具有刚性的非柔性基底材料（112）的柔性基板（112）沿水平方向彼此相邻布置。 包含无机材料（111a，111b，113a，113b）的绝缘层（111,113）覆盖柔性基板（13）和非柔性基材（112），以使至少一部分柔性基板 （13）。 在绝缘层中形成到达柔性基板（13）的导电图案（132,133）的通孔（116,141），延伸到导电图案（132）的导线（117,118,142,143） 133）通过电镀通过通孔（116,141）形成。 在绝缘层（111,113）上层叠上绝缘层（114,115,144,145），形成电路（123,150）。