公开(公告)号：EP2648309A3

公开(公告)日：2018-01-03

申请号：EP12180715.0

申请日：2012-08-16

Applicant: Lite-On Technology Corporation ,  Novero Dabendorf GmbH

Inventor： Scholz, Frank ,  Graf, Stefan ,  Waldschmidt, Andre ,  Lindenstruth, Lars ,  Jung, Marco

IPC: H02J7/00 ,  H02J7/02

CPC classification number: H02J50/10 ,  H01F27/362 ,  H02J7/0027 ,  H02J7/0042 ,  H02J7/025 ,  H05K1/0218 ,  H05K1/0224 ,  H05K1/0227 ,  H05K2201/09254

Abstract: A comb-structured shielding layer and a wireless charging transmitter thereof are provided. The wireless charging module is connected to a power source, has at least one wireless charging coil and at least one comb-structured shielding layer, and is configured to convert alternative current power from the power source to H-field electromagnetic radiations, and wirelessly charges an electronic device. The comb-structured shielding layer is disposed between the wireless charging module and the target electronic device and configured to allow the H-field electromagnetic radiations pass through. The comb-structured shielding layer includes a first area and a second area. The first area is electrically connected to a reference electric potential. The second area is electrically connected to the reference electric potential through the first area, and is configured to shield the E-field electromagnetic radiations but allow the H-field electromagnetic radiations pass through the comb-structured shielding layer.

Abstract translation: 提供梳状结构的屏蔽层及其无线充电发射器。 无线充电模块连接电源，具有至少一个无线充电线圈和至少一个梳状结构的屏蔽层，并且被配置为将来自电源的替代电流电力转换成H场电磁辐射，并且无线充电 一个电子设备。 梳状结构的屏蔽层设置于无线充电模块与目标电子装置之间，并配置为允许H场电磁辐射通过。 梳形结构的屏蔽层包括第一区域和第二区域。 第一区域电连接到参考电位。 第二区域通过第一区域电连接到参考电位，并且被配置为屏蔽E场电磁辐射但允许H场电磁辐射穿过梳状结构屏蔽层。

公开(公告)号：EP3072370B1

公开(公告)日：2017-10-18

申请号：EP14786668.5

申请日：2014-10-21

Applicant: ZF Friedrichshafen AG

Inventor： LASSMANN, Wilfried ,  SPERBER, Michael

IPC: H05K1/02 ,  H01L23/498 ,  H01L23/552

CPC classification number: H05K1/0265 ,  H01L23/49822 ,  H01L23/552 ,  H01L25/16 ,  H01L2924/0002 ,  H05K1/0218 ,  H05K1/0263 ,  H05K1/0298 ,  H05K1/09 ,  H05K2201/0723 ,  H05K2201/09254 ,  H05K2201/09327 ,  H05K2201/09736 ,  H05K2201/10053 ,  H05K2201/10166 ,  H01L2924/00

公开(公告)号：EP3072370A1

公开(公告)日：2016-09-28

申请号：EP14786668.5

申请日：2014-10-21

Applicant: ZF Friedrichshafen AG

Inventor： LASSMANN, Wilfried ,  SPERBER, Michael

IPC: H05K1/02 ,  H01L23/528 ,  F16H61/00 ,  H05K5/00 ,  F02N11/14

CPC classification number: H05K1/0265 ,  H01L23/49822 ,  H01L23/552 ,  H01L25/16 ,  H01L2924/0002 ,  H05K1/0218 ,  H05K1/0263 ,  H05K1/0298 ,  H05K1/09 ,  H05K2201/0723 ,  H05K2201/09254 ,  H05K2201/09327 ,  H05K2201/09736 ,  H05K2201/10053 ,  H05K2201/10166 ,  H01L2924/00

Abstract: The invention relates to a multi-functional high-current circuit board (4) comprising a current conduction multi-layer (12) having a number of thick layers (13, 14, 15, 16) for conducting electrical current, a switching layer (18) having at least one power switch (3) for connecting a consumer (1), a control layer (8) for controlling the at least one power switch (3), said layer having at least one control element (7), and at least one shielding element (13, 16) for shielding the current conduction multi-layer (12) from the control layer (8) and from the switching layer (18).

Abstract translation: 多功能高电流电路板包括具有用于传导电流的多个层的电流传导层，包括用于切换电负载的至少一个电源断路器的开关层，包括至少一个控制元件的控制层，以控制 至少一个电源断路器，用于屏蔽来自控制层和开关层的导电层的至少一个屏蔽元件。

公开(公告)号：EP2869393A4

公开(公告)日：2016-01-27

申请号：EP13813272

申请日：2013-03-28

Applicant: NEC CORP

Inventor： KASAHARA YOSHIAKI ,  TOYAO HIROSHI

IPC: H05K1/02 ,  H01P1/20 ,  H01Q15/00

CPC classification number: H03H7/0161 ,  H01P1/2005 ,  H01P1/203 ,  H01P3/08 ,  H01Q15/0066 ,  H01Q15/008 ,  H03H7/0115 ,  H05K1/0236 ,  H05K1/162 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/09781

Abstract: A second conductor plane (102) is formed in a layer different from a layer in which a first conductor plane (101) is formed, and faces the first conductor plane (101). A first transmission line (104) is formed in a layer different from the layers in which the first conductor plane (101) and the second conductor plane (102) are formed, and faces the second conductor plane (102), and one end thereof is an open end. A conductor via (106) connects the other end of the first transmission line (104) and the first conductor plane (101). An insular conductor (112) is connected to a portion of the first transmission line (104) other than a portion thereof at which the transmission line (104) is attached to the conductor via (106), is located in a layer different from the layer in which the second conductor plane (102) is located, and faces the second conductor plane (102).

公开(公告)号：EP2043153A4

公开(公告)日：2012-08-15

申请号：EP07768243

申请日：2007-07-05

Applicant: HAMAMATSU PHOTONICS KK

Inventor： YONETA YASUHITO ,  SUZUKI HISANORI ,  KOBAYASHI HIROYA ,  MURAMATSU MASAHARU

IPC: H01L27/146 ,  H05K1/02 ,  H05K1/11

CPC classification number: H01L27/14618 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/15192 ,  H05K1/0269 ,  H05K1/0295 ,  H05K1/112 ,  H05K2201/09254 ,  H05K2201/09918 ,  H05K2201/09954 ,  H05K2201/10674 ,  H05K2203/049 ,  H05K2203/166 ,  H01L2924/00014 ,  H01L2924/00012

公开(公告)号：EP2190272A3

公开(公告)日：2012-01-18

申请号：EP09252645.8

申请日：2009-11-18

Applicant: Everlight Electronics Co., Ltd.

Inventor： Chao, Tzu-Hao

IPC: H05K3/32 ,  H05K1/11

CPC classification number: H05K1/181 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09254 ,  H05K2201/09409 ,  H05K2201/10106 ,  Y02P70/611 ,  H01L2924/00

Abstract: A circuit structure (100) of a package carrier (S) including a plurality of chip pads (C), a first electrode (110), a second electrode (120), a third electrode (130) and a fourth electrode (140) are provided. These chip pads are arranged in an M×N array. A first bonding pad (P1), a second bonding pad (P2), a third bonding pad (P3) and a fourth bonding pad (P4) are disposed clockwise in the peripheral area of each chip pad in sequence. The orientations of each of the first, second, third, and fourth bonding pads of the (S-1) th row rotated by 90 degrees are equal to the orientations of each of the first, second, third and fourth bonding pads of the S th row, respectively. The first electrode is connected with each first bonding pad. The second electrode is connected with each second bonding pad. The third electrode is connected with each third bonding pad. The fourth electrode is connected with each fourth bonding pad.

公开(公告)号：EP2187715B1

公开(公告)日：2011-05-04

申请号：EP09252440.4

申请日：2009-10-19

Applicant: Nitto Denko Corporation

Inventor： Ishii, Jun ,  Naitou, Toshiki ,  Honjo, Mitsuru

IPC: H05K1/00 ,  G11B5/48

CPC classification number: H05K3/4685 ,  G11B5/484 ,  G11B5/4853 ,  G11B5/486 ,  H05K1/0228 ,  H05K1/0237 ,  H05K1/0265 ,  H05K1/056 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/0979 ,  Y10T29/49155

公开(公告)号：EP2056342A3

公开(公告)日：2011-04-06

申请号：EP08019270.1

申请日：2008-11-04

Applicant: Hitachi Ltd.

Inventor： Nakazato, Norio c/o Hitachi, Ltd., Intellectual Property Group, ,  Fujieda, Nobuo c/o Hitachi, Ltd., Intellectual Property Group, ,  Ishibashi, Masayoshi c/o Hitachi, Ltd., Intellectual Property Group, ,  Kato, Midori c/o Hitachi, Ltd., Intellectual Property Group, ,  Arai, Tadashi c/o Hitachi, Ltd., Intellectual Property Group, ,  Shiba, Takeo c/o Hitachi, Ltd., Intellectual Property Group,

IPC: H01L21/48

CPC classification number: H01L21/4867 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/09036 ,  H05K2201/09254 ,  H01L2924/00

Abstract: A wiring board (1) with an electronic device comprises a plurality of trenches (10, 13, 73, 74) arranged in parallel on a substrate, a common trench (9, 12, 71, 72) communicating the plurality of trenches with each other at one of their ends on the substrate, a metal layer formed at the bottom of the plurality of trenches, and an electrode layer connected with the metal layer and formed on a bottom of the common trench, wherein the electrode layer on the bottom of the common trench constitutes a source electrode (9, 72) or a drain electrode (12, 71) of a field effect transistor, whereby the wiring board and an electronic circuit having a good fine wire pattern and a good narrow gap between the patterns using a coating material can be formed, and a reduction for a cost of an organic thin filmelectronic device and the electronic circuit can be attained since they can be realized through a development of a printing technique.

Abstract translation: 具有电子器件的布线板（1）包括平行布置在衬底上的多个沟槽（10,13,73,74），连通多个沟槽的公共沟槽（9,12,71,72） 所述多个沟槽的底部形成有金属层，所述金属层与所述金属层连接形成在所述公共沟槽的底部，所述电极层位于所述基板的底部， 公共沟槽构成场效应晶体管的源电极（9,72）或漏电极（12,71），由此布线板和电子电路具有良好的细线图案和使用图案之间良好的窄间隙 可以形成涂层材料，并且可以实现有机薄膜电子器件和电子电路的成本降低，因为它们可以通过印刷技术的发展来实现。

公开(公告)号：EP1698033A4

公开(公告)日：2010-07-21

申请号：EP04817915

申请日：2004-12-22

Applicant: X2Y ATTENUATORS LLC

Inventor： ANTHONY DAVID ,  ANTHONY ANTHONY ,  ANTHONY WILLIAM M ,  MUCCIOLI JAMES ,  NEIFELD RICHARD A

IPC: H02H9/00 ,  H05K1/02

CPC classification number: H01G4/35 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P1/203 ,  H05K1/0233 ,  H05K2201/09254 ,  H05K2201/0969 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/1006 ,  H05K2201/10454 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

公开(公告)号：EP2190272A2

公开(公告)日：2010-05-26

申请号：EP09252645.8

申请日：2009-11-18

Applicant: Everlight Electronics Co., Ltd.

Inventor： Chao, Tzu-Hao

IPC: H05K3/32 ,  H05K1/11

CPC classification number: H05K1/181 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09254 ,  H05K2201/09409 ,  H05K2201/10106 ,  Y02P70/611 ,  H01L2924/00

Abstract: A circuit structure (100) of a package carrier (S) including a plurality of chip pads (C), a first electrode (110), a second electrode (120), a third electrode (130) and a fourth electrode (140) are provided. These chip pads are arranged in an M×N array. A first bonding pad (P1), a second bonding pad (P2), a third bonding pad (P3) and a fourth bonding pad (P4) are disposed clockwise in the peripheral area of each chip pad in sequence. The orientations of each of the first, second, third, and fourth bonding pads of the (S-1) th row rotated by 90 degrees are equal to the orientations of each of the first, second, third and fourth bonding pads of the S th row, respectively. The first electrode is connected with each first bonding pad. The second electrode is connected with each second bonding pad. The third electrode is connected with each third bonding pad. The fourth electrode is connected with each fourth bonding pad.

Abstract translation: 包括多个芯片焊盘（C），第一电极（110），第二电极（120），第三电极（130）和第四电极（140）的封装载体（S）的电路结构（100） 被提供。 这些芯片焊盘以M×N阵列排列。 第一接合焊盘（P1），第二接合焊盘（P2），第三接合焊盘（P3）和第四接合焊盘（P4）顺序地设置在每个芯片焊盘的周边区域中。 旋转90度的第（S-1）行的第一，第二，第三和第四接合焊盘中的每一个的取向等于S的第一，第二，第三和第四焊盘中的每一个的取向 行。 第一电极与每个第一接合焊盘连接。 第二电极与每个第二接合焊盘连接。 第三电极与每个第三接合焊盘连接。 第四电极与每个第四接合焊盘连接。