公开(公告)号：EP1286578A3

公开(公告)日：2006-03-22

申请号：EP02026472.7

申请日：1998-10-12

Applicant: IBIDEN CO., LTD.

Inventor： Asai, Motoo, Ibiden Co., Ldt ,  Shimada, Kenichi, Ibiden Co., Ldt ,  Noda, Kouta, Ibiden Co., Ldt ,  Kayriya, Takashi, Ibiden Co., Ldt ,  Segawa, Hiroshi, Ibiden Co., Ldt

IPC: H05K3/46

CPC classification number: B32B3/00 ,  H05K3/0094 ,  H05K3/383 ,  H05K3/384 ,  H05K3/385 ,  H05K3/4069 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0215 ,  H05K2201/0257 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A multilayer printed wiring board is composed of a substrate (100) provided with through-holes (107), and a wiring board (101) formed on the substrate (100) through the interposition of an interlaminar insulating resin layer (104), the through-holes (107) having a roughened internal surface and being filled with a filler (108), an exposed part of the filler (108) in the through-holes (107) being covered with a through-hole-covering conductor layer (109), and a viahole (102) formed just thereabove being connected to the through-hole-covering conductor layer (109).
Without peeling between the through-holes (107) and the filler (108), this wiring board has a satisfactory connection reliability between the through-holes (107) and the internal layer circuit (103) and provides a high density wiring.

Abstract translation: 一种多层印刷电路板是由通过层间树脂绝缘层（104）的插入而形成在基片（100）的通孔（107）设置有一个基片（100），和一个电路板（101）的，所述 通孔（107）具有粗糙的内表面，并填充有填充材料（108）在所述通孔填充材料（108）（107）的露出部分被覆了通孔的导体层覆盖的（ 109），以及形成的正上方有一个通孔（102）被连接到通孔的导体层覆盖的（109）。 如果没有通孔（107）和所述填料（108）之间的剥离，此电路板具有通孔（107）和所述内层电路（103）之间的满意的连接可靠性，并提供了高密度的布线。

公开(公告)号：EP1091024A4

公开(公告)日：2006-03-22

申请号：EP99917206

申请日：1999-04-28

Applicant: EBARA CORP

Inventor： HONGO AKIHISA ,  NAGAI MIZUKI ,  OHNO KANJI ,  KIMIZUKA RYOICHI ,  MARUYAMA MEGUMI

IPC: C25D3/38 ,  C25D5/10 ,  C25D7/12 ,  H01L21/288 ,  H01L21/768 ,  H05K3/42

CPC classification number: H01L21/76843 ,  C25D3/38 ,  C25D5/10 ,  C25D7/12 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H05K3/423 ,  H05K2201/09563 ,  H05K2203/1476

Abstract: A method and apparatus for plating a substrate is provided, wherein fine pits formed in the substrate, such as fine channels for wiring, are filled with a copper, copper alloy, or other material with low electrical resistance. The method is performed on a wafer W having fine pits (10) to fill the fine pits with a metal (13) and includes performing a first plating process (11) by immersing the wafer in a first plating solution having a composition superior in throwing power; and performing a second plating process (12) by immersing the substrate in a second plating solution having a composition superior in leveling ability.

Abstract translation: 提供了一种用于电镀基板的方法和装置，其中在基板中形成的细凹坑，例如用于布线的细小通道，填充有铜，铜合金或其他具有低电阻的材料。 该方法在具有细凹坑（10）的晶片W上进行，以用金属（13）填充细凹坑，并且包括通过将晶片浸入具有优异投掷成分的第一电镀液中来进行第一电镀工艺（11） 功率; 以及通过将所述基板浸入具有优异的流平能力的组成的第二电镀液中来进行第二电镀工艺（12）。

公开(公告)号：EP1098558A4

公开(公告)日：2006-03-15

申请号：EP99926766

申请日：1999-06-23

Applicant: IBIDEN CO LTD

Inventor： NISHIWAKI YOKO ,  NODA KOUTA

IPC: H05K3/00 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K3/4626 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/0094 ,  H05K3/384 ,  H05K3/385 ,  H05K3/4602 ,  H05K2201/0108 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0278 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/072 ,  H05K2203/1157 ,  Y10T29/49155

Abstract: A multilayer printed wiring board which is constructed such that a conductor circuit (29) is formed on a core substrate (21) via an interlayer resin insulation layer (32), a through hole (23) is provided in the core substrate and a filler (25) is filled in the through hole. The interlayer resin insulation layer on the core substrate is flat and a roughened layer (31) of the same kind is formed on the entire surface including side surfaces of the conductor circuit on the core substrate. A cover plated layer (30) is formed directly above the through hole, a roughened layer is formed on the entire surfaces including side surfaces of this conductor layer and the conductor circuit located in the same layer of the conductor layer, and a flat-surface interlayer resin insulation layer for filling a recess between conductors is formed on the surface of this roughened layer, thereby providing an excellent crack resistance under such conditions as a heat cycle and eliminating a possible damage to the cover plated layer.

Abstract translation: 一种多层印刷线路板，其具有通过层间树脂绝缘层（2）形成有内导体电路图案（4）的芯基板（1）上形成外导体电路图案（5）的结构，以及通孔（9） ）形成在用于将内部导体电路图案（4）彼此电连接的基板中。 填充物（10）填充在通孔（9）中。 在基板（1）上的内部导体电路图案（4）上形成包括其侧表面的整个表面上的相同种类的粗糙层（11）。 形成为覆盖内部导体电路图案（4）的层间树脂绝缘层（2）是平坦的。 外导体电路图案（5）由形成在层间树脂绝缘层（2）上的无电镀层（12）和形成在化学镀层（12）上的电解镀层构成。

公开(公告)号：EP1505859A3

公开(公告)日：2005-02-16

申请号：EP04024664.7

申请日：1999-02-05

Applicant: IBIDEN CO., LTD.

Inventor： Shirai, Seiji ,  Shimada, Kenichi ,  Asai, Motoo

IPC: H05K3/46 ,  H05K3/42

CPC classification number: H05K3/4661 ,  H05K3/108 ,  H05K3/381 ,  H05K3/382 ,  H05K3/421 ,  H05K3/423 ,  H05K2201/0129 ,  H05K2201/015 ,  H05K2201/0278 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09745 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24917 ,  Y10T428/31681

Abstract: The invention provides a multilayer printed wiring board having a filled viahole structure for forming a fine circuit pattern, providing excellent resistance against cracking under a thermal shock. The multilayer printed wiring board is comprised of conductor circuitry layers and interlaminar insulative resin layers having formed through them holes filled with a plating layer to form a viahole. The surface of the plating layer exposed out of the hole for the viahole is formed substantially flat and lies at a substantially same level as the surface of the conductor circuit disposed in the interlaminar insulative resin layer. The thickness of the conductor circuitry layer is less than a half of the viahole diameter and less than 25 µm. The inner wall of the hole formed in the interlaminar insulative resin layer is roughened and an electroless plating layer is deposited on the roughened surface. An electroplating layer is filled in the hole including the electroless plating layer to form the viahole.

Abstract translation: 本发明提供一种多层印刷线路板，其具有用于形成精细电路图案的填充通孔结构，在热冲击下提供优异的抗开裂性。 多层印刷线路板由导体电路层和层间绝缘树脂层构成，其中已形成填充有镀层以形成通孔的孔。 露出用于通孔的孔的镀层的表面形成为基本平坦，并且位于与设置在层间绝缘树脂层中的导体电路的表面基本相同的水平。 导体电路层的厚度小于通孔直径的一半，小于25μm。 形成在层间绝缘树脂层中的孔的内壁变粗糙，并且在粗糙化表面上沉积化学镀层。 在包括无电镀层的孔中填充电镀层以形成通孔。

公开(公告)号：EP1233663B1

公开(公告)日：2004-12-15

申请号：EP02009112.0

申请日：1994-10-28

Applicant: International Business Machines Corporation

Inventor： Arldt, Roy Lynn ,  Boyko, Christina Marie ,  Cayson, Burtan Joe ,  Kozlowski, Richard Michael ,  Kulesza, Joseph Duane ,  Lauffer, John Matthew ,  Liu, Philip Chihchau ,  Markovich, Voya Rista ,  Mahmoud, Issa Said ,  Muska, James Francis ,  Papathomas, Kostas ,  Sabia, Joseph Gene

IPC: H05K3/40 ,  H05K1/16

CPC classification number: H05K1/113 ,  B32B7/04 ,  H01B1/22 ,  H01B1/24 ,  H01L2224/16235 ,  H05K1/095 ,  H05K1/16 ,  H05K1/167 ,  H05K3/0023 ,  H05K3/0047 ,  H05K3/0094 ,  H05K3/4053 ,  H05K3/4069 ,  H05K2201/0347 ,  H05K2201/09563 ,  H05K2201/10734 ,  H05K2203/0126 ,  H05K2203/0191 ,  H05K2203/0207 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0763 ,  Y10S428/901 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24273 ,  Y10T428/24331 ,  Y10T428/24339 ,  Y10T428/24826 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/25

公开(公告)号：EP1377696A1

公开(公告)日：2004-01-07

申请号：EP02714381.7

申请日：2002-03-21

Applicant: Koninklijke Philips Electronics N.V.

Inventor： MEULENKAMP, Eric, A. ,  SCHROEVERS, Maria, J.

IPC: C25D5/10 ,  C25D7/04 ,  H05K3/18

CPC classification number: H01L21/76868 ,  C25D3/38 ,  C25D5/34 ,  C25D7/123 ,  H01L21/288 ,  H01L21/76873 ,  H01L21/76877 ,  H05K3/388 ,  H05K3/389 ,  H05K3/423 ,  H05K2201/0239 ,  H05K2201/0257 ,  H05K2201/09563

Abstract: The invention provides for a back-end metallisation process in which a recess is filled with copper and which includes the step of forming a plating base on the surfaces of the recess for the subsequent galvanic deposition of the said copper, and wherein subsequent to the formation of the plating base, but prior to the galvanic deposition of the copper, a modifying agent is introduced to the recess and which serves to absorb in the surface regions not covered by the plating base and to thereby modify the surface to promote copper growth thereon so as to effectively repair the initial plating base before the copper plating fill commences.

Abstract translation: 本发明提供了一种后端金属化工艺，其中凹槽填充有铜，并且该工艺包括在凹槽的表面上形成用于随后的所述铜的电沉积的电镀基底的步骤，并且其中在形成 ，但是在电沉积铜之前，将改性剂引入到凹槽中，并且该改性剂用于在未被电镀基底覆盖的表面区域中吸收并且由此修饰表面以促进其上的铜生长 以在铜镀层填充开始之前有效修复初始镀层基体。

公开(公告)号：EP0843357B1

公开(公告)日：2003-07-30

申请号：EP97309161.4

申请日：1997-11-13

Applicant: TEXAS INSTRUMENTS INC.

Inventor： Abbott, Donald C.

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0554 ,  H05K2203/1394 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

公开(公告)号：EP1194021A3

公开(公告)日：2003-07-23

申请号：EP01122596.8

申请日：2001-09-26

Applicant: Hitachi, Ltd. ,  NITTO DENKO CORPORATION

Inventor： Suwa, Tokihito, Hitachi Research Laboratory ,  Tanaka, Atsushi ,  Tanigawa, Satoshi ,  Fujii, Hirofumi ,  Mune, Kazunori

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4644 ,  H05K1/09 ,  H05K3/108 ,  H05K3/388 ,  H05K3/423 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0344 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09563 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: To provide a method of producing a multilayer printed wiring board that can be intended to have low-profile, light-weight and high-density wiring of a printed wiring board, and a multilayer printed wiring board produced by the method of producing a multilayer printed wiring board, the double-sided substrate is produced by the steps of forming an insulating resin layer (2) on a metal foil (1); of forming a via hole (3) in the insulating resin layer (2); of forming a first circuit pattern (4) on the insulating resin layer (2) and forming a conductive layer (5) in the via hole (3), by plating; and of etching the metal foil (1) to form it into a second circuit pattern (6). The produced double-sided substrate (7) is used as a core substrate for producing multilayer printed wiring board by a laminate-en-bloc or a build-up method.

公开(公告)号：EP1197130B1

公开(公告)日：2003-05-21

申请号：EP00948103.7

申请日：2000-07-13

Applicant: International Business Machines Corporation

Inventor： LAUFFER, John ,  RUSSELL, David

IPC: H05K1/16 ,  H05K3/46 ,  H01F41/04

CPC classification number: H01F41/041 ,  H01F17/0033 ,  H05K1/095 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/0023 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/0367 ,  H05K2201/086 ,  H05K2201/09563 ,  H05K2201/097 ,  H05K2201/09881 ,  H05K2203/0568 ,  H05K2203/1453 ,  H05K2203/1461 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T428/24917 ,  Y10T428/2495 ,  Y10T428/24967 ,  Y10T428/24975

Abstract: Passive electrical components such as capacitors, resistors, inductors, transformers, filters and resonators are integrated into electrical circuits utilizing a process which maximizes the utilization of the planar surfaces of the substrates for high density placement of active components such as logic or memory integrated circuits. The passive components are integrated into a conventional circuit board utilizing a photoimageable dielectric material (20). The dielectric (20) is photoimaged and etched to provide one or more recesses or openings (26) for the passive devices, and photovias interconnecting the inputs and outputs of the integrated circuit board. The electronic structure comprising at least one of the passive devices integrated into a photoimaged dielectric (20) is described as well as the method of manufacturing the same.

公开(公告)号：EP1310582A1

公开(公告)日：2003-05-14

申请号：EP02257669.8

申请日：2002-11-06

Applicant: Shipley Company LLC

Inventor： Tsuchida, Hideki ,  Kusaka, Masaru ,  Hayashi, Shinjiro ,  Tsukagoshi, Satoru

IPC: C25D3/38 ,  H01L21/768

CPC classification number: C25D3/38 ,  C25D7/12 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423 ,  H05K2201/09563

Abstract: A process for electrolytic copper plating, that is suitable for the formation of filled vias without compromising the brightness of the deposit is provided. In this process, copper electroplating is carried out in the presence of a transition metal oxide.

Abstract translation: 提供了一种电解镀铜方法，其适用于形成填充的通孔而不损害沉积物的亮度。 在该方法中，在过渡金属氧化物的存在下进行铜电镀。