公开(公告)号：EP2293356B1

公开(公告)日：2018-04-04

申请号：EP10165966.2

申请日：2010-06-15

Applicant: Paragon Semiconductor Lighting Technology Co.,Ltd.

Inventor： Peng, Hsin-Yuan ,  Yang, Shen-Ta ,  Chung, Chia-Tin

IPC: H01L33/56 ,  H01L33/60 ,  H01L33/62 ,  H01L33/64 ,  H01L33/00 ,  H01L33/50 ,  H01L33/54 ,  H01L23/31

CPC classification number: H01L33/62 ,  H01L23/3121 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L33/50 ,  H01L33/54 ,  H01L33/56 ,  H01L33/60 ,  H01L33/641 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/48655 ,  H01L2224/73265 ,  H01L2224/838 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01088 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2933/005 ,  H01L2933/0058 ,  H05K3/244 ,  H05K2201/10106 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An LED package structure for increasing heat-dissipating and light-emitting efficiency includes a substrate unit, an alloy unit, a light-emitting unit, a conductive unit and a package unit. The substrate unit has a substrate body, a first conductive pad, a second conductive pad and a chip-placing pad. The alloy unit has a Ni/Pd alloy formed on the chip-placing pad. The light-emitting unit has an LED chip positioned on the Ni/Pd alloy of the alloy unit by solidified solder ball or glue. The conductive unit has two conductive wires, and the LED chip is electrically connected to the first conductive pad and the second conductive pad by the two conductive wires, respectively. The package unit has a light-transmitting package gel body formed on the top surface of the substrate body in order to cover the light-emitting unit and the conductive unit.

公开(公告)号：EP2727145A2

公开(公告)日：2014-05-07

申请号：EP12807500.9

申请日：2012-07-03

Applicant: Eoplex Limited

Inventor： ROGREN, Philip, E.

IPC: H01L23/498 ,  H01L23/495

CPC classification number: H01L21/4828 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/4866 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48684 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4886 ,  H01L2224/48864 ,  H01L2224/48869 ,  H01L2224/48884 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/8546 ,  H01L2224/85464 ,  H01L2224/85469 ,  H01L2224/85484 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A lead carrier provides support for a semiconductor device during manufacture. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a die attach pad surrounded by a plurality of terminal pads. The pads are formed of a fusible fixing material on a lower portion. A chip is mounted upon the die attach pad and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be heated above a melting temperature of the fusible fixing material and peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronics system board.

Abstract translation: 引线载体在制造期间为半导体器件提供支撑。 引线架包括具有多个封装位置的临时支撑构件。 每个包装部位包括由多个端子焊盘包围的管芯附接焊盘。 焊盘由下部的可熔固定材料形成。 芯片安装在管芯附着焊盘上，引线接合从芯片延伸到端子焊盘。 焊盘，芯片和引线键都被封装在模具化合物内。 临时支撑构件可以被加热到可熔固定材料的熔化温度以上并被剥离，然后将各个封装位置彼此隔离，以提供包括用于安装在电子系统板内的多个表面安装接头的完整的封装。

公开(公告)号：EP2273544A2

公开(公告)日：2011-01-12

申请号：EP10183317.6

申请日：2001-12-14

Applicant: STMicroelectronics S.r.l.

Inventor： Tiziani, Roberto ,  Passagrilli, Carlo

IPC: H01L21/60 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05083 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor electronic device (1) is disclosed, which comprises a die (2) of semiconductor material and a support (3), the die (2) of semiconductor material including an integrated electronic circuit and a plurality of contact pads (6) associated with the electronic circuit and connected electrically to the support (3) by wire leads (4), each contact pad of said plurality of contact pads (6) comprising a lower layer (7) of copper, or alloys thereof; and an upper layer. Advantageously, the upper layer consists of:
a first film (9) of nickel or alloys thereof, overlying the lower layer (7) of copper or alloys thereof;
a second film of palladium or alloys thereof, overlying the first film (9) of nickel or alloys thereof; and optionally
a third film (10) of gold or alloys thereof, overlying the second film of palladium or alloys thereof.
Moreover, the layer or film (9, 10) are deposited by an electroless chemical process.

Abstract translation: 一种半导体电子设备（1）的光盘游离缺失，其包括半导体材料和载体（2）（3），半导体材料制成，包括上集成电子电路和接触垫多个管芯（2）（6）相关联的 与由引线的电子电路和电连接到所述支撑件（3）（4），包括：下位层的接触焊盘，所述多个（6）的每一个接触垫铜，或其合金的（7）; 并在上层。 有利的是，上层的组成：镍或合金的第一膜（9）它们的，覆盖在下层（7）铜或其合金的; 钯或合金的第二膜体，覆镍或它们的合金的第一膜（9）; 和任选的金或合金的第三电影（10）它们的，上覆钯或其合金的第二电影。 更完了，层或膜（9,10）是在通过无电解化学工艺沉积。

公开(公告)号：EP2235751A1

公开(公告)日：2010-10-06

申请号：EP08870490.3

申请日：2008-12-24

Applicant: Linear Technology Corporation

Inventor： PRUITT, David

IPC: H01L23/495

CPC classification number: H01L23/49562 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05655 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48655 ,  H01L2224/48855 ,  H01L2224/49431 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a die support structure which includes a die paddle integral with a first set of contacts and a second set of contacts that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to contacts in succession by alternate ball and wedge bonds on each contacts. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires. The wires, which preferably are made of copper, then may be bonded to the electrically conductive layer by melting the solder paste, preferably by heating the support structure, allowing the solder to reflow and wet the wires, and then cool to produce a low resistance mass between the leads.

公开(公告)号：EP1909325A1

公开(公告)日：2008-04-09

申请号：EP06781411.1

申请日：2006-07-21

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： KITABATAKE, Makoto, Matsushita Electric Ind. Co.,Ltd. ,  KUSUMOTO, Osamu, Matsushita Electric Ind. Co.,Ltd. ,  UCHIDA, Masao, Matsushita Electric Ind. Co.,Ltd. ,  YAMASHITA, Kenya, Matsushita Electric Ind. Co.,Ltd.

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/06 ,  H01L29/12 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L29/7806 ,  H01L23/62 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/7811 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48666 ,  H01L2224/4868 ,  H01L2224/48724 ,  H01L2224/48755 ,  H01L2224/48766 ,  H01L2224/4878 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48744

Abstract: A semiconductor element (20) of the present invention includes a plurality of field effect transistors (90) and a schottky electrode (9a), and the schottky electrode (9a) is formed along an outer periphery of a region where the plurality of field effect transistors (90) are formed.

Abstract translation: 本发明的半导体元件（20）包括多个场效应晶体管（90）和肖特基电极（9a），肖特基电极（9a）沿着多个场效应区域的外周形成 形成晶体管（90）。

公开(公告)号：EP1313142A3

公开(公告)日：2006-05-10

申请号：EP02257723.3

申请日：2002-11-07

Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.

Inventor： Ito, Daisuke ,  Kazama, Takuya

IPC: H01L23/485

CPC classification number: H01L24/03 ,  H01L23/525 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/00

Abstract: In a semiconductor device manufacturing method embodying the present invention for forming a rerouting layer (30), which has wirings (29) for electrically leading electrode terminals (23) and bonding pads (28), on a major surface side (20a) on which the electrode terminals (23) of a semiconductor element (20) are provided, the wirings (29) are formed thinner than the bonding pads (28).

公开(公告)号：EP1615267A1

公开(公告)日：2006-01-11

申请号：EP04727676.1

申请日：2004-04-15

Applicant: DENKI KAGAKU KOGYO KABUSHIKI KAISHA

Inventor： YONEMURA, Naomi, c/o Denki Kagaku Kogyo KK ,  YASHIMA, Katunori, c/o Denki Kagaku Kogyo KK ,  TSUJIMURA, Yoshihiko, c/o Denki Kagaku Kogyo KK ,  ISHIKURA, Hidenori, c/o Denki Kagaku Kogyo KK ,  SAIKI, Takashi, c/o Denki Kagaku Kogyo KK

IPC: H01L23/12 ,  H01L25/04 ,  H05K1/05 ,  H05K3/44

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L23/142 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05666 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/4516 ,  H01L2224/45166 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48472 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48666 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48766 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4886 ,  H01L2224/48866 ,  H01L2224/4911 ,  H01L2224/85411 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/8546 ,  H01L2224/85466 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01061 ,  H01L2924/01063 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/19051 ,  H01L2924/30105 ,  H05K1/0224 ,  H05K1/024 ,  H05K1/025 ,  H05K3/0061 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09745 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48811 ,  H01L2224/48824 ,  H01L2224/48744 ,  H01L2224/4876 ,  H01L2224/4866

Abstract: To provide a metal base circuit board excellent in heat dissipation properties, which remarkably reduces malfunction time of a semiconductor which occurs when a hybrid integrated circuit is operated at a high frequency.
A metal base circuit board to be use for a hybrid integrated circuit, comprising circuits provided on a metal plate via an insulating layer (A, B), a power semiconductor mounted on the circuit and a control semiconductor to control the power semiconductor, provided on the circuit, wherein a low capacitance portion is embedded under a circuit portion (pad portion) on which the control semiconductor is mounted, preferably, the low capacitance portion is made of a resin containing an inorganic filler and has a dielectric constant of from 2 to 9.

Abstract translation: 提供一种金属基底电路板具有优异的散热性，从而降低了其中当混合集成电路以高频率操作的发生半导体的显着故障时间。 的金属基底电路板是使用用于混合集成电路，在绝缘层，其包括通过提供在金属板上的电路（A，B），功率半导体安装在所述电路和控制半导体控制功率半导体，设置在上 的电路中，worin低电容部分嵌入的电路部分在其上的控制半导体安装，优选地，低电容部分由含无机填料的树脂的，并且具有2至的介电常数（焊盘部）下 9日

公开(公告)号：EP1139413B1

公开(公告)日：2005-03-16

申请号：EP01000048.7

申请日：2001-03-09

Applicant: Texas Instruments Incorporated

Inventor： Test, Howard R. ,  Amador, Gonzalo ,  Subido, Willmar E.

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L23/53238 ,  H01L21/288 ,  H01L23/53233 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/0568 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/4868 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/4878 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/4888 ,  H01L2224/85013 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/3025 ,  H01L2924/01004 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2224/48869 ,  H01L2224/48744

公开(公告)号：EP1176640A3

公开(公告)日：2004-03-17

申请号：EP01000318.4

申请日：2001-07-27

Applicant: Texas Instruments Incorporated

Inventor： Efland, Taylor R ,  Pendharkar, Sameer

IPC: H01L23/485 ,  H01L23/528

CPC classification number: H01L24/48 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/5286 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01037 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2924/20755 ,  H01L2924/00015 ,  H01L2924/2075

Abstract: A semiconductor integrated circuit comprises contact pads located over active components, which are positioned to minimize the distance for power delivery between a selected pad and one or more corresponding active components, to which the power is to be delivered. This minimum distance further enhances dissipation of thermal energy released by the active components. More specifically, a semiconductor integrated circuit comprises a laterally organized power transistor, an array of power supply contact pads distributed over the transistor, means for providing a distributed, predominantly vertical current flow from the contact pads to the transistor, and means for connecting a power source to each of the contact pads. Positioning the power supply contact pads directly over the active power transistor further saves precious silicon real estate area. The means for vertical current flow include contact pads made of a stack of metal layers comprising refractory metals for adhesion, copper and nickel as stress-absorbing metals, and gold or palladium as bondable and solderable outermost metals. The means for connecting a power source include wire bonding and solder ball interconnection.

公开(公告)号：EP1146552A3

公开(公告)日：2003-04-16

申请号：EP01303322.0

申请日：2001-04-09

Applicant: Agere Systems Guardian Corporation

Inventor： Moyer, Ralph Salvatore ,  Ryan, Vivian Wanda

IPC: H01L21/60 ,  H01L23/532 ,  H01L23/485

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/0347 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05655 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4554 ,  H01L2224/45572 ,  H01L2224/45573 ,  H01L2224/45655 ,  H01L2224/45666 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48655 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48755 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/20302 ,  H01L2924/20303 ,  H01L2924/20304 ,  H01L2924/20305 ,  H01L2924/20306 ,  H01L2924/20307 ,  H01L2924/20308 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2224/45644 ,  H01L2924/01004 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/01006

Abstract: The specification describes a process for forming a barrier layer (21,22) on copper metallization (13) in semiconductor integrated circuits. The barrier layer is effective for both wire bond and solder bump interconnections. The barrier layer is Ti/Ni formed on the copper. Aluminum bond pads are formed on the barrier layer for wire bond interconnections and copper bond pads are formed on the barrier layer for solder bump interconnections.