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    Semiconductor device
    24.
    发明专利
    Semiconductor device 有权
    半导体器件

    公开(公告)号：JP2014135506A

    公开(公告)日：2014-07-24

    申请号：JP2014050609

    申请日：2014-03-13

    申请人： Renesas Electronics Corp ,  ルネサスエレクトロニクス株式会社

    发明人： NAKASHIBA YASUTAKA

    IPC分类号： H01L21/822 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L27/04

    CPC分类号： H01L23/585 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/00

    摘要： PROBLEM TO BE SOLVED: To solve the problem that transmission characteristics in wiring becomes unstable in a conventional semiconductor device.SOLUTION: A semiconductor device 1 comprises: wiring 10; and a dummy conductor pattern 20. The wiring 10 is the wiring in which current having a frequency of 5 GHz or higher flows. The dummy conductor pattern 20 is disposed in the vicinity of the wiring 10. A planar shape of the dummy conductor pattern 20 is equal to a diagram having an interior angle of exceeding 180°.

    摘要翻译： 要解决的问题：为了解决传统半导体器件中布线的传输特性变得不稳定的问题。解决方案：半导体器件1包括：布线10; 和虚设导体图案20.布线10是流过频率为5GHz以上的电流的布线。 虚设导体图案20配置在配线10的附近。虚设导体图案20的平面形状与内角超过180°的图形相同。

    Semiconductor device
    27.
    发明专利
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：JP2013183120A

    公开(公告)日：2013-09-12

    申请号：JP2012047803

    申请日：2012-03-05

    申请人： Elpida Memory Inc ,  エルピーダメモリ株式会社

    发明人： IDE AKIRA

    IPC分类号： H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

    CPC分类号： H01L23/481 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/15311

    摘要： PROBLEM TO BE SOLVED: To enhance the bonding strength among semiconductor chips of a stacked semiconductor device.SOLUTION: A semiconductor device includes a plurality of through electrodes TSV provided so as to penetrate through semiconductor chips and arranged along an a-a line. The plurality of through electrodes TSV include dummy through electrodes TSVd nearest a side L23 of the semiconductor chips. The dummy through electrodes TSVd are not connected to an internal circuit and have a floating state. According to the present invention, providing the dummy through electrodes TSVd enhances the bonding strength among the plurality of stacked semiconductor chips. For this reason, the use of the semiconductor chips according to the present invention can enhance the reliability of a stacked semiconductor device.

    摘要翻译： 要解决的问题：提高叠层半导体器件的半导体芯片之间的接合强度。解决方案：半导体器件包括多个穿过半导体芯片并沿着a-a线布置的贯穿电极TSV。 多个贯通电极TSV包括最靠近半导体芯片的侧面L23的虚设通孔电极TSVd。 虚拟通电极TSVd不连接到内部电路并具有浮置状态。 根据本发明，提供虚拟通孔电极TSVd提高了多个层叠半导体芯片之间的接合强度。 因此，根据本发明的半导体芯片的使用可以提高叠层半导体器件的可靠性。

    Fuse bus for plating feature on semiconductor die
    30.
    发明专利
    Fuse bus for plating feature on semiconductor die 有权
    FUSE总线用于半导体器件上的功能

    公开(公告)号：JP2013026624A

    公开(公告)日：2013-02-04

    申请号：JP2012159145

    申请日：2012-07-18

    申请人： Freescale Semiconductor Inc ,  フリースケール セミコンダクター インコーポレイテッド

    发明人： GEORGE R LEAL ,  KEVIN J HESS ,  TRET S YULIN

    IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/522

    CPC分类号： H01L23/585 ,  H01L23/5256 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03001 ,  H01L2224/05556 ,  H01L2224/45124 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/03

    摘要： PROBLEM TO BE SOLVED: To provide a method of electroplating a feature structure such as an interconnection part or a bond pad on a semiconductor die.SOLUTION: The method comprises the steps of: forming a plurality of fuses (208) over a semiconductor substrate; and forming a plurality of interconnection layers (400-408) over the semiconductor substrate and a plurality of interconnection pads (502) on upper surfaces of the plurality of interconnection layers. A seal ring (202) is formed around an active circuit formed in and on the semiconductor substrate (302), the plurality of interconnection pads (502), and the plurality of fuses (208, 320). Each fuse (208, 320) is electrically connected to a corresponding interconnection pad (502) and the seal ring (202). When each fuse (208) is in a conductive state, the fuse electrically connects the corresponding interconnection pad (502) to the seal ring (202).

    摘要翻译： 要解决的问题：提供在半导体管芯上电镀诸如互连部件或接合焊盘的特征结构的方法。 解决方案：该方法包括以下步骤：在半导体衬底上形成多个保险丝（208）; 以及在所述半导体衬底上形成多个互连层（400-408）和在所述多个互连层的上表面上的多个互连焊盘（502）。 密封环（202）围绕形成在半导体衬底（302）上的有源电路，多个互连焊盘（502）和多个保险丝（208,320）形成。 每个熔丝（208,320）电连接到相应的互连焊盘（502）和密封环（202）。 当每个熔断器（208）处于导通状态时，保险丝将相应的互连焊盘（502）电连接到密封环（202）。 版权所有（C）2013，JPO＆INPIT