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    Semiconductor device and memory card using the same
    63.
    发明专利
    Semiconductor device and memory card using the same 有权
    半导体器件和使用其的存储卡

    公开(公告)号：JP2007293800A

    公开(公告)日：2007-11-08

    申请号：JP2006277884

    申请日：2006-10-11

    Applicant: Toshiba Corp ,  株式会社東芝

    Inventor： OKADA TAKASHI ,  OKADA KIYOKAZU ,  ONO AKINORI ,  NISHIYAMA HIROSHI

    IPC: G06K19/077

    CPC classification number: H05K1/0256 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/181 ,  H05K1/117 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/0761 ,  H05K2201/09145 ,  H05K2201/09227 ,  H05K2203/0228 ,  H01L2924/00012 ,  H01L2924/00014

    Abstract: PROBLEM TO BE SOLVED: To avoid a decrease in insulation between wires and a deterioration in the characteristics of a semiconductor element or the like due to the effect of heating during cutting, when a curved part is provided in the outer form of a semiconductor device. SOLUTION: An external connecting terminal 8 is provided on the first principal plane 2a of a circuit board 2 and semiconductor elements 13, 14 are mounted on a second principal plane 2b. A first wiring network 9 is provided on the first principal plane 2a of the circuit board 2 except where the external connecting terminal 8 is formed. A second wiring network 11 is provided on the second principal plane 2b of the circuit board 2. The wiring networks 9, 11 are formed further away from a side 4A having a notch part 5 and a constricted part 6 including a curved part than from other sides (3A, 3B, 4B). COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题为了避免由于在切割期间加热的影响导致的导线之间的绝缘的降低和半导体元件等的特性的劣化，当弯曲部分设置在外部形式 半导体器件。

    解决方案：外部连接端子8设置在电路板2的第一主平面2a上，半导体元件13,14安装在第二主平面2b上。 除了形成外部连接端子8之外，第一布线网络9设置在电路板2的第一主平面2a上。 第二布线网络11设置在电路板2的第二主平面2b上。布线网络9,11形成为更远离具有切口部分5的侧面4A和包括弯曲部分的收缩部分6 （3A，3B，4B）。 版权所有（C）2008，JPO＆INPIT

    How to increase the routing density for the circuit board and such a circuit board
    64.
    发明专利
    How to increase the routing density for the circuit board and such a circuit board 审中-公开

    公开(公告)号：JP2007520888A

    公开(公告)日：2007-07-26

    申请号：JP2006551992

    申请日：2005-02-03

    Applicant: コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ

    Inventor： ジャオ，リリィ ,  ロー，マイケル

    IPC: H05K3/46 ,  H01L23/498 ,  H01L23/50 ,  H05K1/11

    CPC classification number: H05K1/114 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/10734 ,  Y10T29/49155 ,  H01L2924/00

    Abstract: 第一層（２０１）と、第一層（２０１）と実質的に平行な第四層（２０４）とから成る多層回路基板（ＭＰＣＢ）が開示される。 複数の電気接点（２０７ａａ，２０７ｃａ，２０７ｅａ，２０７ｂｂ，２０７ｄｂ，２０７ａｃ，２０７ｃｃ，２０７ｅｃ，２０７ｂｄ，２０７ｄｄ，２０７ｂａ，２０７ｄａ，２０７ａｂ，２０７ｃｂ，２０７ｅｂ，２０７ｂｃ，２０７ｄｃ，２０７ａｄ，２０７ｃｄ，２０７ｅｄ；３１１）が、多層回路基板の第一層（２０１）上に形成され、第一グリッド内に配置される。 複数の電気接点は、第一層内の経路指定のための第一サブセット（２０７ａａ，２０７ｃａ，２０７ｅａ，２０７ｂｂ，２０７ｄｂ，２０７ａｃ，２０７ｃｃ，２０７ｅｃ，２０７ｂｄ，２０７ｄｄ）と、第四層内の経路指定のための第二サブセット（２０７ｂａ，２０７ｄａ，２０７ａｂ，２０７ｃｂ，２０７ｅｂ，２０７ｂｃ，２０７ｄｃ，２０７ａｄ，２０７ｃｄ，２０７ｅｄ）とに分割される。 複数のビア（２１０ａａ，２０１ｂａ，２０１ａｂ，２０１ｂｂ，２０１ｂｃ，２０１ａｃ，２０１ｂｃ，２０１ａｄ，２０１ｂｄ，２０１ｃｄ）が、第一層（２０１）と第四層（２０４）との間に形成され、それぞれ前記複数の電気接点の第二サブセットの少なくとも１つに隣接して配置され、複数のビア（２１０ａａ，２０１ｂａ，２０１ａｂ，２０１ｂｂ，２０１ｂｃ，２０１ａｃ，２０１ｂｃ，２０１ａｄ，２０１ｂｄ，２０１ｃｄ）は、複数の電気接点の隣接する電気接点間の最小間隔よりも大きなそれらの各対の間の間隔を有する。

    Multi-terminal device and printed wiring board
    65.
    发明专利
    Multi-terminal device and printed wiring board 有权
    多终端设备和打印接线板

    公开(公告)号：JP2006128633A

    公开(公告)日：2006-05-18

    申请号：JP2005262986

    申请日：2005-09-09

    Applicant: Canon Inc ,  キヤノン株式会社

    Inventor： AISAKA TORU

    IPC: H01L23/12 ,  H05K3/46

    CPC classification number: H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/10734 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To permit wiring on a printed wiring board at a low cost, even in the case when high-speed differential signal pins are arranged in the direction of the inner periphery of a BGA. SOLUTION: In a multi-terminal device 1 in which many connection terminals are planarly arranged on one face, terminals 3 that are not required to be individually, electrically connected are arranged between the differential signal terminals 2 of the multi-terminal device and the edge of the multi-terminal device. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：即使在高速差分信号引脚布置在BGA的内周方向的情况下，也可以低成本地布线在印刷电路板上。 解决方案：在多端子装置1中，其中许多连接端子平面布置在一个面上，不需要单独地电连接的端子3被布置在多端子装置的差动信号端子2之间 和多终端设备的边缘。 版权所有（C）2006，JPO＆NCIPI

    Printed wiring board
    66.
    发明专利
    Printed wiring board 有权
    印刷线路板

    公开(公告)号：JP2005340506A

    公开(公告)日：2005-12-08

    申请号：JP2004157425

    申请日：2004-05-27

    Applicant: Fuji Xerox Co Ltd ,  富士ゼロックス株式会社

    Inventor： IGUCHI DAISUKE

    IPC: H05K1/02 ,  H05K3/46

    CPC classification number: H05K1/0245 ,  H05K1/0248 ,  H05K1/025 ,  H05K2201/09227 ,  H05K2201/09727 ,  H05K2201/09827

    Abstract: PROBLEM TO BE SOLVED: To provide a printed wiring board for suppressing such an adverse influence as the deterioration of transmission quality due to the mismatching of the differential impedance of a differential transmission line.
    SOLUTION: This printed wiring board 10 is mounted with a driver element 20 for outputting a differential signal and a receiver element 22 for inputting the differential signal, and they are connected through differential signal wiring 24. The differential signal wiring 24 is constituted of a first wiring 24A and a second wiring 24B. The widths of the terminals of the first wiring 24A and the second wiring 24B are set so as to be the same as those of electrode pads 26A and 26B while the widths are gradually reduced according as they go from one end side to the other end side, and from the other end side to one end side. The first wiring 24A and the second wiring 24B are formed so as to be made close so that their wiring intervals can be made narrow, and formed so as to be turned into parallel lines at positions where their width becomes predetermined width.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于抑制由于差分传输线的差分阻抗不匹配而导致的传输质量下降的不利影响的印刷线路板。 解决方案：该印刷电路板10安装有用于输出差分信号的驱动元件20和用于输入差分信号的接收器元件22，并且它们通过差分信号布线24连接。构成差分信号布线24 的第一布线24A和第二布线24B。 第一布线24A和第二布线24B的端子的宽度被设定为与电极焊盘26A和26B相同，同时宽度随着从一端侧到另一端侧逐渐减小 ，从另一端侧到一端侧。 第一布线24A和第二布线24B形成为使得它们的布线间隔可以变窄，并且形成为在宽度变为预定宽度的位置处变成平行线。 版权所有（C）2006，JPO＆NCIPI

    Multilayer wiring board
    67.
    发明专利
    Multilayer wiring board 有权
    多层接线板

    公开(公告)号：JP2005236091A

    公开(公告)日：2005-09-02

    申请号：JP2004044306

    申请日：2004-02-20

    Applicant: Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

    Inventor： HIRAKAWA HIDEKAZU

    IPC: H05K3/46 ,  H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H05K1/11

    CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/10674

    Abstract: PROBLEM TO BE SOLVED: To contribute to the improvement of a yield as a product and to the reduction of cost by effectively reducing the number of laminations of multilayer wiring boards, in providing the "multilayer wiring board" on which an electronic component in which electrodes are arranged as a lattice at a mounting surface side is mounted. SOLUTION: In the wiring layer of the first layer of the multilayer wiring board, a wiring pattern WP is led out of pads P1 of the outermost periphery in a pad arrangement region PR 1, pads P2 located on a diagonal line near the corner of the region and pads P3 located in a slant direction at a part between lines which adjoin each other inside the region. In wiring layers after the second layer, out of pads which are electrically connected through viaholes to pads from which the wiring pattern WP is not led out in the upper wiring layer, the wiring pattern WP is led out of pads P1 of the outermost periphery in a pad arrangement region PR 2 and pads P3 located in a slant direction at a part between lines which adjoin each other inside the region PR2. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题为了有助于提高产品的成品率和降低成本，通过有效地减少多层布线板的叠片数量，在提供电子部件的“多层布线基板” 电极在安装面侧安装为格子。 解决方案：在多层布线板的第一层的布线层中，将布线图案WP从焊盘布置区域PR 1中的最外周的焊盘P1引出，位于邻近的对角线上的焊盘P2 该区域的角部和位于该区域内彼此相邻的线之间的部分处的倾斜方向的垫P3。 在第二层之后的布线层中，从通过通孔与电连接的焊盘焊接到布线图案WP不从上布线层引出的焊盘，布线图案WP从最外周的焊盘P1引出 焊盘布置区域PR2和在区域PR2内彼此相邻的线之间的部分处的倾斜方向的焊盘P3。 版权所有（C）2005，JPO＆NCIPI

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