公开(公告)号：JP5296313B2

公开(公告)日：2013-09-25

申请号：JP2006518914

申请日：2004-07-08

Applicant: インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： ベドナー、トーマス、アール ,  グールド、スコット、ダブリュ ,  ラッキー、デイヴィッド、イー ,  スタウト、ダグラス、ダブリュ ,  ズコウスキー、ポール、エス

IPC: H01L21/82 ,  G06F9/45 ,  H01L20060101 ,  H01L23/528 ,  H01L27/02 ,  H03K19/00

CPC classification number: H01L23/5286 ,  G11C5/14 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit. The integrated circuit includes a parent terrain; and a hierarchical order of nested voltage islands within the parent terrain, each higher-order voltage island nested within a lower-order voltage island, each nested voltage island having the same hierarchical structure.

公开(公告)号：JP5281748B2

公开(公告)日：2013-09-04

申请号：JP2006542811

申请日：2004-12-06

Applicant: インターナショナル レクティフィアー コーポレイション

Inventor： ビーチ・ロバート

IPC: H01L21/28 ,  H01L20060101 ,  H01L21/338 ,  H01L29/417 ,  H01L29/47 ,  H01L29/739 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872 ,  H01L31/0328

CPC classification number: H01L29/7786 ,  H01L21/28581 ,  H01L21/28587 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/452 ,  H01L29/66143 ,  H01L29/66462 ,  H01L29/861 ,  H01L29/872 ,  H01L29/88 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

公开(公告)号：JP5281682B2

公开(公告)日：2013-09-04

申请号：JP2011183879

申请日：2011-08-25

Applicant: ロベルト・ボッシュ・ゲゼルシャフト・ミト・ベシュレンクテル・ハフツングRobert Bosch Gmbh

Inventor： パートリッジ，アーロン ,  ルッツ，マルクス ,  クローンミュラー，ズィルヴィア

IPC: B81C1/00 ,  H01L20060101 ,  H01L21/44 ,  H01L23/06 ,  H01L23/28 ,  H01L23/48 ,  H01L23/52 ,  H01L27/14 ,  H01L29/40 ,  H01L29/82 ,  H01L29/84

CPC classification number: B81C1/00261 ,  B81B2207/015 ,  B81C1/00333 ,  B81C2201/0176 ,  B81C2203/0136 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide.

公开(公告)号：JP5248770B2

公开(公告)日：2013-07-31

申请号：JP2006507509

申请日：2004-03-24

Applicant: メルク パテント ゲーエムベーハー

Inventor： ゴーディアナ、ラッセル ,  ディ． エッカート、ロバート ,  モンテロ、アラン ,  モンテロ、エドムンド

IPC: H01M14/00 ,  H01G9/20 ,  H01L20060101 ,  H01L27/30 ,  H01L31/00 ,  H01L31/04 ,  H01L51/42 ,  H01L51/44

CPC classification number: H01L27/301 ,  H01G9/2013 ,  H01G9/2031 ,  H01G9/2059 ,  H01G9/2068 ,  H01G9/2081 ,  H01L51/4253 ,  H01L51/441 ,  H01L51/445 ,  Y02E10/542 ,  Y02E10/549 ,  Y02P70/521

Abstract: In one aspect, the invention provides photovoltaic cells that utilize a mesh electrode on at least one exposure side of the photovoltaic cell. Preferably, the mesh electrode is a metallic mesh. In one embodiment, the invention provides dye-sensitized solar cells (DSSC) having a wire mesh exposure side electrode and a photovoltaic material comprising a photosensitized interconnected nanoparticle layer. In one embodiment, the wire mesh electrode functions as the cathode of the DSSC. In another embodiment, the wire mesh electrode functions as the anode of the DSSC. In addition, embodiments are provided where wire mesh electrodes are used for the anode and the cathode of a DSSC.

公开(公告)号：JP5202842B2

公开(公告)日：2013-06-05

申请号：JP2006517574

申请日：2004-06-23

Applicant: リー,サン−ユン

Inventor： リー，サン−ユン

IPC: H01L27/00 ,  H01L20060101 ,  H01L21/30 ,  H01L21/301 ,  H01L21/331 ,  H01L21/336 ,  H01L21/338 ,  H01L21/46 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L29/47 ,  H01L29/73 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/812 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872 ,  H01L31/072

CPC classification number: B82Y10/00 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/10805 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/228 ,  H01L27/2454 ,  H01L28/55 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/8613 ,  H01L29/872

公开(公告)号：JP5160895B2

公开(公告)日：2013-03-13

申请号：JP2007542017

申请日：2005-11-23

Applicant: イムベラ エレクトロニクス オサケユキチュア

Inventor： トーオミネン リスト ,  イーホ−ラ アンティ

IPC: H01L23/12 ,  H01L20060101 ,  H01L21/48 ,  H01L21/60 ,  H01L21/68 ,  H01L23/498 ,  H01L23/538 ,  H05K1/18 ,  H05K3/42

CPC classification number: H05K1/188 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83132 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/3511 ,  H05K3/42 ,  H05K2201/0355 ,  H05K2201/10674 ,  Y10T29/49002 ,  Y10T29/49126 ,  H01L2924/00

Abstract: Method for manufacturing an electronic module, which electronic module includes a component (6), which has contact areas (17), which are connected electrically to a conductor-pattern layer (14). The manufacture according to the method starts from a layered membrane, which comprises at least a conductor layer (4) and an insulator layer (10) on the first surface of the conductor layer (4). Contact openings (17), the mutual positions of which correspond to the mutual positions of the contact areas (7) of the component (6), and which penetrate both the conductor layer (4) and the insulator layer (10), are made in the membrane. After the manufacture of the contact openings (17), the component (6) is attached to the surface of the insulator layer (10), in such a way that the contact areas (7) of the component (6) line up next to the contact openings (17). After this, at least in the contact openings (17) and the contact areas (7) of the component (6) a conductor material is made, which connects the component (6) to the conductor layer (4) and the conductor layer (4) is patterned to form a conductor-pattern layer (14).

Abstract translation: 电子模块的制造方法，该电子模块包括具有接触区域（17）的部件（6），该接触区域电连接到导体图案层（14）。 根据该方法的制造从在导体层（4）的第一表面上至少包括导体层（4）和绝缘体层（10）的层状膜开始。 使其相互位置对应于部件（6）的接触区域（7）并且穿过导体层（4）和绝缘体层（10）的相互位置的接触开口（17）被制成 在膜中。 在制造接触开口（17）之后，组件（6）以这样一种方式附接到绝缘体层（10）的表面上，使得部件（6）的接触区域（7） 接触开口（17）。 此后，至少在部件（6）的接触开口（17）和接触区域（7）中，制成导体材料，其将部件（6）连接到导体层（4）和导体层（ 4）被图案化以形成导体图案层（14）。

公开(公告)号：JP2012231165A

公开(公告)日：2012-11-22

申请号：JP2012153053

申请日：2012-07-06

Applicant: Asm America Inc ,  エーエスエム アメリカ インコーポレイテッド

Inventor： MATTHIAS BAUER

IPC: H01L21/20 ,  C30B1/00 ,  H01L20060101 ,  H01L21/02 ,  H01L21/265 ,  H01L21/76 ,  H01L27/12

CPC classification number: H01L21/02381 ,  H01L21/02488 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/84

Abstract: PROBLEM TO BE SOLVED: To provide methods for producing SiGe-on-insulator structures and for forming strain-relaxed SiGe layers on silicon while minimizing defects.SOLUTION: Amorphous SiGe layers 600 are deposited on at least one monolayer of a dopant by CVD from trisilane and GeH. The amorphous SiGe layers 600 are recrystallized over silicon by melt or solid phase epitaxy (SPE) processes. The melt processes preferably also cause diffusion of germanium to dilute the overall germanium content and essentially consume silicon 500 overlying an insulator. The SPE process can be conducted with or without diffusion of germanium into the underlying silicon 500, and so is applicable to SOI as well as conventional semiconductor substrates.

Abstract translation: 要解决的问题：提供用于制造绝缘体上硅结构并在硅上形成应变松弛SiGe层的方法，同时使缺陷最小化。 解决方案：非晶SiGe层600通过CVD从丙硅烷和GeH 4 沉积在掺杂剂的至少一个单层上。 非晶SiGe层600通过熔融或固相外延（SPE）工艺在硅上重结晶。 熔融方法优选还引起锗的扩散以稀释总锗含量，并且基本上消耗覆盖在绝缘体上的硅500。 SPE工艺可以在有或没有锗扩散到下面的硅500的情况下进行，因此也适用于SOI以及常规的半导体衬底。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP5016771B2

公开(公告)日：2012-09-05

申请号：JP2002500457

申请日：2001-06-01

Applicant: サイテク エレクトロ オプティクス アクチボラゲット

Inventor： リンドホルム、ラルス

IPC: H01L31/16 ,  G01B11/03 ,  H01L20060101 ,  H01L31/00 ,  H01L31/02 ,  H01L31/0328 ,  H01L31/10 ,  H01L31/11

CPC classification number: H01L31/1105 ,  H01L31/02024

公开(公告)号：JP2012147457A

公开(公告)日：2012-08-02

申请号：JP2012046081

申请日：2012-03-02

Applicant: Broadlogic Network Technologies Inc ,  ブロードロジック ネットワーク テクノロジーズ インコーポレイテッド

Inventor： ZHANG WEIMIN ,  LIO BINFAN ,  WANG ZHONGQIANG

IPC: H04N7/32 ,  G06K9/36 ,  H01L20060101 ,  H04N5/00 ,  H04N5/272 ,  H04N7/12 ,  H04N7/26 ,  H04N7/30 ,  H04N7/50

CPC classification number: H04N21/2362 ,  H04N19/174 ,  H04N19/423 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61 ,  H04N21/40

Abstract: PROBLEM TO BE SOLVED: To provide an MPEG decoder capable of effectively handling video processing.SOLUTION: According to one aspect of an MPEG processor, multiple MPEG data streams for corresponding channels are individually stored in an off-chip memory. Corresponding data for a channel is then read from the off-chip memory for processing. The read data is then decoded, and decoded results and associated information are stored in the off-chip memory. Some or all of the associated information that can be used for decoding subsequent data is stored in an on-chip memory. When video images need to be displayed, the corresponding data that is needed for that purpose is read from the off-chip memory, provided to an analog encoder, and encoded in a format that is compatible with an analog display device.

Abstract translation: 要解决的问题：提供能够有效处理视频处理的MPEG解码器。 解决方案：根据MPEG处理器的一个方面，用于相应通道的多个MPEG数据流被单独存储在片外存储器中。 然后从片外存储器中读出通道的对应数据进行处理。 然后对读取的数据进行解码，将解码结果和相关信息存储在片外存储器中。 可用于解码后续数据的部分或全部相关信息存储在片上存储器中。 当需要显示视频图像时，从芯片内存中读取为此目的所需的相应数据，提供给模拟编码器，并以与模拟显示设备兼容的格式进行编码。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2012134535A

公开(公告)日：2012-07-12

申请号：JP2012047250

申请日：2012-03-02

Applicant: Lam Research Corporation ,  ラム リサーチ コーポレーションLam Research Corporation

Inventor： REN DAXING

IPC: H01L21/3065 ,  C23C16/44 ,  H01J37/32 ,  H01L20060101 ,  H01L21/00 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/67069 ,  C23C16/4405 ,  C23C16/4407 ,  H01J37/32477 ,  H01J2237/022

Abstract: PROBLEM TO BE SOLVED: To provide a silicon carbide part of a plasma processing apparatus which allows the reduction of particle contamination on a semiconductor substrate.SOLUTION: The method comprises: the step of heating a silicon carbide part at a temperature of about 750 or 1200°C or processing the part by oxygen plasma to remove a free carbon making a cause of particle contamination from at least the surface of the part produced by reaction between silicon vapor and carbon, provided that the silicon carbide part is used for a lower-side baffle plate 22a of a showerhead electrode 10 of a semiconductor substrate processing apparatus.

Abstract translation: 要解决的问题：提供允许减少半导体衬底上的颗粒污染的等离子体处理装置的碳化硅部分。 解决方案：该方法包括：在约750℃或1200℃的温度下加热碳化硅部件或通过氧等离子体处理该部件以除去至少从表面引起颗粒污染的游离碳的步骤 通过硅蒸汽和碳之间的反应产生的部分，只要碳化硅部分用于半导体衬底处理装置的喷头电极10的下侧挡板22a即可。 版权所有（C）2012，JPO＆INPIT