-
1.发明授权Chip scale package with electronic component received in encapsulant, and fabrication method thereof 有权具有接收在密封剂中的电子部件的芯片级封装及其制造方法公开(公告)号：US09040361B2
公开(公告)日：2015-05-26
申请号：US12959148
申请日：2010-12-02
CPC分类号： H01L24/82 , H01L23/3128 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/73 , H01L25/105 , H01L2224/12105 , H01L2224/24225 , H01L2224/25171 , H01L2224/32155 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/3511
摘要： A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.
摘要翻译： CSP包括：具有带导电焊盘的第一布线层的硬板; 布置在所述导电垫的至少一部分上的多个导电元件; 电子元件具有相反的有源和无效表面，并且经由非活性表面安装在硬板上; 设置在所述硬板上用于封装所述导电元件和电子部件的封装层，所述电子部件的所述有源表面和所述导电元件的表面通过所述封装层露出; 设置在所述封装层上的第一电介质层和第三布线层，所述第三布线层电连接到所述导电元件和所述电子部件，并且还通过所述导电元件与所述第一布线层电连接，从而获得堆叠连接结构 不需要PTH和使用硬板作为主要结构，以避免翘曲。
-
公开(公告)号：US08525348B2
公开(公告)日：2013-09-03
申请号：US12971797
申请日：2010-12-17
IPC分类号： H01L23/48
CPC分类号： H01L25/50 , H01L21/561 , H01L24/19 , H01L24/20 , H01L24/96 , H01L25/105 , H01L2224/02379 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/12105 , H01L2224/13022 , H01L2224/13099 , H01L2224/16221 , H01L2224/211 , H01L2224/221 , H01L2224/73267 , H01L2224/83191 , H01L2224/92244 , H01L2224/96 , H01L2225/1035 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/12 , H01L2924/14 , H01L2924/3511 , H05K1/185 , H05K3/4644 , H01L2924/00014 , H01L2224/19 , H01L2224/11
摘要： A fabrication method of a chip scale package includes providing electronic components, each having an active surface with electrode pads and an opposite inactive surface, and a hard board with a soft layer disposed thereon; adhering the electronic components to the soft layer via the inactive surfaces thereof; pressing the electronic components such that the soft layer encapsulates the electronic components while exposing the active surfaces thereof; forming a dielectric layer on the active surfaces of the electronic components and the soft layer; and forming a first wiring layer on the dielectric layer and electrically connected to the electrode pads, thereby solving the conventional problems caused by directly attaching a chip on an adhesive film, such as film-softening, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the electrode pads and the wiring layer formed in a subsequent RDL process and even waste product.
摘要翻译： 芯片级封装的制造方法包括提供电子元件，每个电子元件具有带有电极焊盘的活动表面和相对的无效表面，以及设置有软层的硬板; 通过其无效表面将电子部件粘附到软层; 按压电子部件，使得软层在暴露其活性表面的同时封装电子部件; 在电子部件和软质层的有源面上形成介电层; 并且在电介质层上形成第一布线层并与电极焊盘电连接，从而解决了直接将芯片附着在粘合膜上的常规问题，例如膜软化，密封剂溢出，翘曲，芯片偏移和污染 导致在随后的RDL工艺中形成的电极焊盘和布线层之间的电连接不良甚至废物。
-
公开(公告)号：US20120061825A1
公开(公告)日：2012-03-15
申请号：US12906501
申请日：2010-10-18
IPC分类号： H01L23/498 , H01L21/50
CPC分类号： H01L23/3114 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/5389 , H01L24/19 , H01L24/82 , H01L2224/04105 , H01L2224/12105 , H01L2224/16235 , H01L2224/20 , H01L2224/82001 , H01L2225/1035 , H01L2225/1058 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/18162
摘要： A chip scale package and a method of fabricating the chip scale package. The chip scale package includes a encapsulant having a first surface and a second surface opposing the first surface; a conductive pillar formed in the encapsulant and exposed from the first surface and the second surface; a chip embedded in the encapsulant while exposed from the first surface; a dielectric layer formed on the first surface, the conductive pillar and the chip; a circuit layer formed on the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer electrically connecting the circuit layer, electrode pads and the conductive pillar; and a solder mask layer formed on the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure.
摘要翻译： 一种芯片级封装和一种制造芯片级封装的方法。 芯片级封装包括具有第一表面和与第一表面相对的第二表面的密封剂; 形成在所述密封剂中并从所述第一表面和所述第二表面露出的导电柱; 在从第一表面暴露的同时嵌入密封剂中的芯片; 形成在所述第一表面上的电介质层，所述导电柱和所述芯片; 形成在电介质层上的电路层; 形成在电连接电路层，电极焊盘和导电柱的电介质层中的多个导电盲孔; 以及形成在电介质层和电路层上的焊料掩模层，从而根据需要使用导电柱来与其他电子器件外部连接以形成堆叠结构。
-
公开(公告)号：US20120032347A1
公开(公告)日：2012-02-09
申请号：US12971797
申请日：2010-12-17
CPC分类号： H01L25/50 , H01L21/561 , H01L24/19 , H01L24/20 , H01L24/96 , H01L25/105 , H01L2224/02379 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/12105 , H01L2224/13022 , H01L2224/13099 , H01L2224/16221 , H01L2224/211 , H01L2224/221 , H01L2224/73267 , H01L2224/83191 , H01L2224/92244 , H01L2224/96 , H01L2225/1035 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/12 , H01L2924/14 , H01L2924/3511 , H05K1/185 , H05K3/4644 , H01L2924/00014 , H01L2224/19 , H01L2224/11
摘要： A fabrication method of a chip scale package includes providing electronic components, each having an active surface with electrode pads and an opposite inactive surface, and a hard board with a soft layer disposed thereon; adhering the electronic components to the soft layer via the inactive surfaces thereof; pressing the electronic components such that the soft layer encapsulates the electronic components while exposing the active surfaces thereof; forming a dielectric layer on the active surfaces of the electronic components and the soft layer; and forming a first wiring layer on the dielectric layer and electrically connected to the electrode pads, thereby solving the conventional problems caused by directly attaching a chip on an adhesive film, such as film-softening, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the electrode pads and the wiring layer formed in a subsequent RDL process and even waste product.
摘要翻译： 芯片级封装的制造方法包括提供电子元件，每个电子元件具有带有电极焊盘的活动表面和相对的无效表面，以及设置有软层的硬板; 通过其无效表面将电子部件粘附到软层; 按压电子部件，使得软层在暴露其活性表面的同时封装电子部件; 在电子部件和软质层的有源面上形成介电层; 并且在电介质层上形成第一布线层并与电极焊盘电连接，从而解决了直接将芯片粘附在粘合膜上的常规问题，例如膜软化，密封剂溢出，翘曲，芯片偏离和污染 导致在随后的RDL工艺中形成的电极焊盘和布线层之间的电连接不良甚至废物。
-
公开(公告)号：US20120313243A1
公开(公告)日：2012-12-13
申请号：US13221323
申请日：2011-08-30
IPC分类号： H01L23/498 , H01L23/48
CPC分类号： H01L23/3128 , H01L23/3114 , H01L24/19 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2924/18162
摘要： A chip-scale package includes an encapsulating layer, a chip embedded in the encapsulating layer and having an active surface exposed from the encapsulating layer, a buffering dielectric layer formed on the encapsulating layer and the chip, a build-up dielectric layer formed on the buffering dielectric layer, and a circuit layer formed on the build-up dielectric layer and having conductive blind vias penetrating the build-up dielectric layer and being in communication with the openings of the buffering dielectric layer and electrically connected to the chip, wherein the build-up dielectric layer and the buffering dielectric layer are made of different materials. Therefore, delamination does not occur between the buffering dielectric layer and the encapsulating layer, because the buffering dielectric layer is securely bonded to the encapsulating layer and the buffering dielectric layer is evenly distributed on the encapsulating layer.
摘要翻译： 芯片级封装包括封装层，嵌入封装层中的芯片，并且具有从封装层露出的有源表面，形成在封装层和芯片上的缓冲电介质层，形成在封装层上的积聚介电层 缓冲电介质层和形成在积聚电介质层上的电路层，并且具有穿透积聚介电层并且与缓冲电介质层的开口连通并且电连接到芯片的导电盲孔，其中构建 介电层和缓冲电介质层由不同的材料制成。 因此，缓冲电介质层和封装层之间不会发生分层，因为缓冲电介质层牢固地结合到封装层，并且缓冲电介质层均匀地分布在封装层上。
-
公开(公告)号：US08304665B2
公开(公告)日：2012-11-06
申请号：US12266674
申请日：2008-11-07
申请人： Chiang-Cheng Chang , Yen-Ping Wang , Don-Son Jiang , Jeng-Yuan Lai , Yu-Po Wang
发明人： Chiang-Cheng Chang , Yen-Ping Wang , Don-Son Jiang , Jeng-Yuan Lai , Yu-Po Wang
CPC分类号： H05K1/116 , H05K1/114 , H05K2201/09545 , H05K2201/09563
摘要： A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.
摘要翻译： 提出了具有无地导电迹线的封装衬底，其包括形成在其中的多个电镀通孔的芯层和形成在芯层的至少表面上的多个导电迹线。 每个导电迹线具有连接端，接合焊盘端和连接连接端和接合焊盘端的基体，导电迹线通过连接端电连接到相应的一个电镀通孔，以及 连接端具有大于基体的宽度，但不大于电镀通孔的直径，从而增加导电迹线和电镀通孔之间的接触面积，并且防止导电迹线的接触表面与 电镀通孔破裂。
-
公开(公告)号：US20120038044A1
公开(公告)日：2012-02-16
申请号：US12959148
申请日：2010-12-02
IPC分类号： H01L23/488 , H01L21/44
CPC分类号： H01L24/82 , H01L23/3128 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/73 , H01L25/105 , H01L2224/12105 , H01L2224/24225 , H01L2224/25171 , H01L2224/32155 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/3511
摘要： A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.
摘要翻译： CSP包括：具有带导电焊盘的第一布线层的硬板; 布置在所述导电垫的至少一部分上的多个导电元件; 电子元件具有相反的有源和无效表面，并且经由非活性表面安装在硬板上; 设置在所述硬板上用于封装所述导电元件和电子部件的封装层，所述电子部件的所述有源表面和所述导电元件的表面通过所述封装层露出; 设置在所述封装层上的第一电介质层和第三布线层，所述第三布线层电连接到所述导电元件和所述电子部件，并且还通过所述导电元件与所述第一布线层电连接，从而获得堆叠连接结构 不需要PTH和使用硬板作为主要结构，以避免翘曲。
-
公开(公告)号：US20120001328A1
公开(公告)日：2012-01-05
申请号：US12967844
申请日：2010-12-14
IPC分类号： H01L23/498 , H01L21/78
CPC分类号： H01L23/3128 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/181 , H01L2924/3511 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： A chip-sized package and a fabrication method thereof are provided. The method includes forming a protection layer on an active surface of a chip and attaching a non-active surface of the chip to a carrier made of a hard material; performing a molding process and removing a protection layer from the chip; performing an RDL process to prevent problems as encountered in the prior art, such as softening of adhesive films, an encapsulant overflow, a pliable chip and chip deviation or contamination caused by directly adhering the active surface of the chip to the adhesive film that may even lead to inferior electrical contacts between a circuit layer and a plurality of chip bond pads during subsequent RDL process, and cause the package to be scraped. Further, the carrier employed in this invention can be repetitively used in the process to help reduce manufacturing costs.
摘要翻译： 提供了一种芯片尺寸的封装及其制造方法。 该方法包括在芯片的有源表面上形成保护层，并将芯片的非活性表面附着到由硬质材料制成的载体上; 执行模制过程并从芯片去除保护层; 执行RDL处理以防止现有技术中遇到的问题，例如粘合剂膜的软化，密封剂溢出，柔韧的芯片和芯片偏差或由将芯片的活性表面直接粘附到甚至可能粘合的粘合剂膜引起的污染 在随后的RDL处理期间导致电路层和多个芯片接合焊盘之间的较差的电接触，并导致封装被刮除。 此外，本发明中使用的载体可以在该过程中重复使用以帮助降低制造成本。
-
公开(公告)号：US20090283303A1
公开(公告)日：2009-11-19
申请号：US12266674
申请日：2008-11-07
申请人： Chiang-Cheng Chang , Yen-Ping Wang , Don-Son Jiang , Jeng-Yuan Lai , Yu-Po Wang
发明人： Chiang-Cheng Chang , Yen-Ping Wang , Don-Son Jiang , Jeng-Yuan Lai , Yu-Po Wang
IPC分类号： H05K1/09
CPC分类号： H05K1/116 , H05K1/114 , H05K2201/09545 , H05K2201/09563
摘要： A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.
摘要翻译： 提出了具有无地导电迹线的封装衬底，其包括形成在其中的多个电镀通孔的芯层和形成在芯层的至少表面上的多个导电迹线。 每个导电迹线具有连接端，接合焊盘端和连接连接端和接合焊盘端的基体，导电迹线通过连接端电连接到相应的一个电镀通孔，以及 连接端具有大于基体的宽度，但不大于电镀通孔的直径，从而增加导电迹线和电镀通孔之间的接触面积，并且防止导电迹线的接触表面与 电镀通孔破裂。
-
10.发明申请Nickel/gold pad structure of semiconductor package and fabrication method thereof 审中-公开半导体封装的镍/金焊盘结构及其制造方法公开(公告)号：US20060049516A1
公开(公告)日：2006-03-09
申请号：US11145318
申请日：2005-06-03
申请人： Yu-Po Wang , Chiang-Cheng Chang , Chien-Te Chen
发明人： Yu-Po Wang , Chiang-Cheng Chang , Chien-Te Chen
IPC分类号： H01L23/48
CPC分类号： H05K3/243 , H01L21/563 , H01L23/49811 , H01L2924/0002 , H05K1/111 , H05K3/064 , H05K3/3452 , H05K2201/09845 , H05K2203/0542 , Y02P70/611 , H01L2924/00
摘要： A nickel/gold (Ni/Au) pad structure of a semiconductor package and a fabrication method thereof are provided. The fabrication method includes preparing a core layer; forming a conductive trace layer on the core layer; patterning the conductive trace layer to form at least one pad of the conductive trace layer; applying a conductive layer; forming a photoresist layer to define a predetermined plating region on the pad, wherein the predetermined plating region is smaller in area than the pad; forming a Ni/Au layer on the predetermined plating region; removing the photoresist layer and etching away the conductive layer; and applying a solder mask layer and forming at least one opening in the solder mask layer to expose the pad, wherein the opening is larger in area than the Ni/Au layer. The Ni/Au pad structure fabricated by the above method can prevent a solder extrusion effect incurred in the conventional technology.
摘要翻译： 提供半导体封装的镍/金（Ni / Au）焊盘结构及其制造方法。 制造方法包括制备芯层; 在芯层上形成导电迹线层; 图案化导电迹线层以形成至少一个导电迹线层的焊盘; 施加导电层; 形成光致抗蚀剂层以在所述焊盘上限定预定的镀覆区域，其中所述预定电镀区域的面积小于所述焊盘; 在预定的电镀区上形成Ni / Au层; 去除光致抗蚀剂层并蚀刻掉导电层; 以及施加焊接掩模层并在所述焊料掩模层中形成至少一个开口以露出所述焊盘，其中所述开口面积大于所述Ni / Au层。 通过上述方法制造的Ni / Au焊盘结构可以防止传统技术中引起的焊料挤出效应。
-
-
-
-
-
-
-
-
-
搜索结果
17 条记录 (耗时 0.022 秒)
