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    ACCELERATOR CONTROLLER HUB
    3.
    发明申请
    ACCELERATOR CONTROLLER HUB 有权

    公开(公告)号：US20210042254A1

    公开(公告)日：2021-02-11

    申请号：US17083200

    申请日：2020-10-28

    申请人： Pratik Marolia ,  Andrew Herdrich ,  Rajesh Sankaran ,  Rahul Pal ,  David Puffer ,  Sayantan Sur ,  Ajaya Durg

    发明人： Pratik Marolia ,  Andrew Herdrich ,  Rajesh Sankaran ,  Rahul Pal ,  David Puffer ,  Sayantan Sur ,  Ajaya Durg

    IPC分类号： G06F13/40 ,  G06F13/42

    摘要： Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.

    REDUCING THE OVERHEAD ASSOCIATED WITH FREQUENCY CHANGES IN PROCESSORS
    6.
    发明申请
    REDUCING THE OVERHEAD ASSOCIATED WITH FREQUENCY CHANGES IN PROCESSORS 审中-公开
    减少与处理器中频率变化相关的OVERHEAD

    公开(公告)号：US20140122916A1

    公开(公告)日：2014-05-01

    申请号：US13664511

    申请日：2012-10-31

    申请人： Guadalupe J. Garcia ,  Lakshminarayan K. Jagannathan ,  David Puffer

    发明人： Guadalupe J. Garcia ,  Lakshminarayan K. Jagannathan ,  David Puffer

    IPC分类号： G06F1/08

    CPC分类号： G06F1/08 ,  G06F1/324 ,  Y02D10/126

    摘要： In many cases, processors may change frequency sufficiently often to result in significant performance and power consumption losses. These performance and power consumption losses may be mitigated by changing the frequency using a squashing technique rather than using a phase locked loop technique. The squashing technique involves simply eliminated clock pulses to reduce the frequency. This can be done more quickly, resulting in less overhead in some cases.

    摘要翻译： 在许多情况下，处理器可能会频繁地频繁地改变频率，从而导致显着的性能和功耗损失。 这些性能和功耗损失可以通过使用压扁技术改变频率而不是使用锁相环技术来减轻。 挤压技术简单地消除了时钟脉冲以降低频率。 这可以更快地完成，在某些情况下导致更少的开销。

    Buffer management via non-data symbol processing for a point to point link
    9.
    发明申请
    Buffer management via non-data symbol processing for a point to point link 审中-公开
    通过点对点链接的非数据符号处理进行缓冲管理

    公开(公告)号：US20050144341A1

    公开(公告)日：2005-06-30

    申请号：US10750013

    申请日：2003-12-31

    申请人： Daren Schmidt ,  David Puffer ,  Sarath Kotamreddy ,  Lyonel Renaud

    发明人： Daren Schmidt ,  David Puffer ,  Sarath Kotamreddy ,  Lyonel Renaud

    IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F3/00

    CPC分类号： G06F5/14

    摘要： A number of symbols are received in a first integrated circuit (IC) device, where these symbols have been transmitted by a second IC device and are received over a serial point to point link. These symbols include a non-data sequence that has been inserted into a data sequence by the second device. The symbols are loaded into a buffer. The data sequence and some of the non-data sequence is unloaded from the buffer, according to a changing unload pointer. To prevent overflow of the buffer, and in response to detecting the non-data sequence, the unload pointer is changed by more than one entry so that a non-data symbol of the non-data sequence as loaded in the buffer is skipped while unloading from the buffer. In another embodiment, to prevent underflow of the buffer, the unload pointer is stalled at an entry of the buffer that contains a non-data symbol while unloading. Other embodiments are also described and claimed.

    摘要翻译： 在第一集成电路（IC）装置中接收多个符号，其中这些符号已由第二IC器件传输并通过串行点对点链接接收。 这些符号包括已被第二设备插入到数据序列中的非数据序列。 符号被加载到缓冲区。 根据改变的卸载指针，数据序列和一些非数据序列从缓冲区中卸载。 为了防止缓冲器的溢出，并且响应于检测到非数据序列，卸载指针由多个条目改变，使得在卸载期间跳过加载在缓冲器中的非数据序列的非数据符号 从缓冲区。 在另一个实施例中，为了防止缓冲器的下溢，卸载指针在卸载期间在包含非数据符号的缓冲器的条目处被停止。 还描述和要求保护其他实施例。