公开(公告)号：US20140015116A1

公开(公告)日：2014-01-16

申请号：US14008457

申请日：2011-12-16

Applicant: Peng Fu ,  Shan Luo ,  Zhong Lu ,  Kaiyou Qian ,  Chin Tien Chiu ,  Cheeman Yu ,  Hem Takiar ,  Ye Bai

Inventor： Peng Fu ,  Shan Luo ,  Zhong Lu ,  Kaiyou Qian ,  Chin Tien Chiu ,  Cheeman Yu ,  Hem Takiar ,  Ye Bai

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L23/4334 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/5442 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A memory device including a metallic layer shielding electromagnetic radiation and/or dissipating heat, and a method of making the memory device, are disclosed. The metallic layer is formed on a metallic layer transfer assembly. The metallic layer transfer assembly and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the metallic layer is transferred from the shield to the encapsulated memory device.

Abstract translation: 公开了一种包括屏蔽电磁辐射和/或耗散热的金属层的存储器件，以及制造存储器件的方法。 金属层形成在金属层转移组件上。 将金属层转移组件和未封装的存储器件放置在模具中并封装。 在模塑料的包封和固化期间，金属层从屏蔽转移到封装的存储器件。

公开(公告)号：US08324090B2

公开(公告)日：2012-12-04

申请号：US12338787

申请日：2008-12-18

Applicant: Yuri Masuoka ,  Peng-Fu Hsu ,  Huan-Tsung Huang ,  Kuo-Tai Huang ,  Yong-Tian Hou ,  Carlos H. Diaz

Inventor： Yuri Masuoka ,  Peng-Fu Hsu ,  Huan-Tsung Huang ,  Kuo-Tai Huang ,  Yong-Tian Hou ,  Carlos H. Diaz

IPC: H01L21/4763 ,  H01L25/11 ,  H01L29/78

CPC classification number: H01L29/4925 ,  H01L21/28061 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底，提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，形成第一覆盖层和 第二覆盖层覆盖在高k电介质层上，覆盖第一区域的第一覆盖层和覆盖第二区域的第二封盖层，在第一和第二覆盖层上形成含有硅（Si）的层，形成金属层 所述层包含Si，并且在所述第一区域上形成第一栅极堆叠，并且在所述第二有源区域上形成第二栅极堆叠。 第一栅极堆叠包括高k电介质层，第一覆盖层，含有Si的层，金属层和第二栅极堆叠包括高k电介质层，第二覆盖层，含有Si的层和 金属层。

公开(公告)号：US20120193802A1

公开(公告)日：2012-08-02

申请号：US13019126

申请日：2011-02-01

Applicant: Chin-Tien Chiu ,  Chih-Chin Liao ,  Peng Fu

Inventor： Chin-Tien Chiu ,  Chih-Chin Liao ,  Peng Fu

IPC: H01L23/48

CPC classification number: H01L23/24 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor package is disclosed including a substrate, a solder mask layer, one or more semiconductor die mounted to the solder mask layer and electrically coupled to the substrate, and a glob top cover over the semiconductor die. The solder mask further includes a dam protruding above surrounding areas of the solder mask layer and a cavity recessed into the solder mask layer for limiting flow of the glob top cover when the glob top material is applied.

Abstract translation: 公开了一种半导体封装，其包括衬底，焊接掩模层，安装到焊料掩模层并电耦合到衬底的一个或多个半导体管芯以及半导体管芯上的球顶盖。 焊料掩模还包括突出在焊料掩模层的周围区域上方的坝体和凹入焊料掩模层中的空腔，用于限制球形顶盖材料施加时球体顶盖的流动。

公开(公告)号：US07875547B2

公开(公告)日：2011-01-25

申请号：US11035325

申请日：2005-01-12

Applicant: Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Nien Su ,  Peng-Fu Hsu ,  Hun-Jan Tao

Inventor： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Nien Su ,  Peng-Fu Hsu ,  Hun-Jan Tao

IPC: H01L21/4763

CPC classification number: H01L21/76802 ,  H01L21/76835

Abstract: Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.

Abstract translation: 公开了形成接触孔结构的方法和结构。 这些方法首先在衬底上形成基本上无硅的材料层。 在基本无硅材料层上形成材料层。 在基本无硅的材料层和材料层内形成接触孔，而基本上不损坏衬底。 此外，在接触孔中形成导电层以形成接触结构。

公开(公告)号：US07531399B2

公开(公告)日：2009-05-12

申请号：US11532308

申请日：2006-09-15

Applicant: Fong-Yu Yen ,  Cheng-Lung Hung ,  Peng-Fu Hsu ,  Vencent S. Chang ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

Inventor： Fong-Yu Yen ,  Cheng-Lung Hung ,  Peng-Fu Hsu ,  Vencent S. Chang ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

IPC: H01L21/8238

CPC classification number: H01L29/513 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/518

Abstract: A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.

Abstract translation: 公开了一种半导体器件，包括：衬底; 第一高k电介质层; 由不同的高k材料形成的第二高k电介质层; 和金属门。 在另一种形式中，公开了一种形成半导体器件的方法，包括：提供衬底; 在所述衬底上形成第一高k电介质层; 在所述第一介电层上形成不同高k材料的第二电介质层; 以及在所述第二电介质层上形成栅极结构。 在另一种形式中，公开了一种形成半导体器件的方法，其包括：提供衬底; 在基底上形成界面层; 在界面层上形成第一高k电介质层; 进行氮化技术; 进行退火; 在所述第一介电层上形成不同高k材料的第二高k电介质层; 以及在所述第二电介质层上方形成金属栅极结构。

公开(公告)号：US20080173947A1

公开(公告)日：2008-07-24

申请号：US11656711

申请日：2007-01-23

Applicant: Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  K. T. Huang ,  Tze-Liang Lee

Inventor： Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  K. T. Huang ,  Tze-Liang Lee

IPC: H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。 第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。 第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

公开(公告)号：US07378713B2

公开(公告)日：2008-05-27

申请号：US11552704

申请日：2006-10-25

Applicant: Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

Inventor： Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

IPC: H01L27/092 ,  H01L29/423

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

Abstract: Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.

Abstract translation: 具有双金属栅极结构的半导体器件及其制造方法。 提供了具有由绝缘层分隔开的第一掺杂区域和第二掺杂区域的半导体衬底。 在第一掺杂区上形成第一金属栅叠层，在第二掺杂区上形成第二金属栅叠层。 密封层设置在第一栅极堆叠和第二栅极叠层的侧壁上。 第一金属栅叠层包括界面层，界面层上的高k电介质层，高k电介质层上的第一金属层，第一金属层上的金属插入层，金属上的第二金属层 插入层和第二金属层上的多晶硅层。 第二金属栅堆叠包括界面层，界面层上的高k电介质层，高k电介质层上的第二金属层和第二金属层上的多晶硅层。

公开(公告)号：US20080093675A1

公开(公告)日：2008-04-24

申请号：US11583634

申请日：2006-10-18

Applicant: Liang-Gi Yao ,  Shiang-Bau Wang ,  Huan-Just Lin ,  Peng-Fu Hsu ,  Jin Ying ,  Hun-Jan Tao

Inventor： Liang-Gi Yao ,  Shiang-Bau Wang ,  Huan-Just Lin ,  Peng-Fu Hsu ,  Jin Ying ,  Hun-Jan Tao

IPC: H01L29/76

CPC classification number: H01L21/823835 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and a contact etch stop layer (CESL) having a stress over the protection layer and extending over the gate stack.

Abstract translation: 半导体结构包括衬底，衬底上的栅极堆叠，与栅极堆叠相邻的源极/漏极区域，源极/漏极区域上的源极/漏极硅化物区域，源极/漏极硅化物区域上的保护层，其中 栅极叠层上的区域基本上没有保护层，以及在保护层上方并且在栅极堆叠上延伸的接触蚀刻停止层（CESL）。

公开(公告)号：US20060063386A1

公开(公告)日：2006-03-23

申请号：US10949128

申请日：2004-09-23

Applicant: Jang-Shiang Tsai ,  Yi-Nien Su ,  Chung-Chi Ko ,  Jyu-Horng Shieh ,  Peng-Fu Hsu ,  Hun-Jan Tao

Inventor： Jang-Shiang Tsai ,  Yi-Nien Su ,  Chung-Chi Ko ,  Jyu-Horng Shieh ,  Peng-Fu Hsu ,  Hun-Jan Tao

IPC: H01L21/302

CPC classification number: H01L21/02063 ,  G03F7/427 ,  Y10S438/958

Abstract: A plasma processing operation uses a gas mixture of N2 and H2 to both remove a photoresist film and treat a low-k dielectric material. The plasma processing operation prevents degradation of the low-k material by forming a protective layer on the low-k dielectric material. Carbon from the photoresist layer is activated and caused to complex with the low-k dielectric, maintaining a suitably high carbon content and a suitably low dielectric constant. The plasma processing operation uses a gas mixture with H2 constituting at least 10%, by volume, of the gas mixture.

Abstract translation: 等离子体处理操作使用N 2和H 2的气体混合物去除光致抗蚀剂膜并处理低k电介质材料。 等离子体处理操作通过在低k电介质材料上形成保护层来防止低k材料的劣化。 来自光致抗蚀剂层的碳被激活并与低k电介质复合，保持适当高的碳含量和合适的低介电常数。 等离子体处理操作使用构成气体混合物的至少10体积％的H 2 N 2气体混合物。

公开(公告)号：US07012027B2

公开(公告)日：2006-03-14

申请号：US10766596

申请日：2004-01-27

Applicant: Baw-Ching Perng ,  Yuan-Hung Chiu ,  Mei-Hui Sung ,  Peng-Fu Hsu

Inventor： Baw-Ching Perng ,  Yuan-Hung Chiu ,  Mei-Hui Sung ,  Peng-Fu Hsu

IPC: H01L21/31

CPC classification number: H01L21/3065 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66583

Abstract: A method is described for selectively etching a high k dielectric layer that is preferably a hafnium or zirconium oxide, silicate, nitride, or oxynitride with a selectivity of greater than 2:1 relative to silicon oxide, polysilicon, or silicon. The plasma etch chemistry is comprised of one or more halogen containing gases such as CF4, CHF3, CH2F2, CH3F, C4F8, C4F6, C5F6, BCl3, Br2, HF, HCl, HBr, HI, and NF3 and leaves no etch residues. An inert gas or an inert gas and oxidant gas may be added to the halogen containing gas. In one embodiment, a high k gate dielectric layer is removed on portions of an active area in a MOS transistor. Alternatively, the high k dielectric layer is used in a capacitor between two conducting layers and is selectively removed from portions of an ILD layer.

Abstract translation: 描述了一种相对于氧化硅，多晶硅或硅选择性地蚀刻优选为铪或氧化锆，硅酸盐，氮化物或氮氧化物的高k电介质层的方法，其选择性大于2:1。 等离子体蚀刻化学性质由一种或多种含卤素气体组成，例如CF 4，CH 3 3，CH 2 F 2， CH 3，CH 3，CH 3，CH 3，CH 3，CH 3，CH 3， C 5，C 5，F 5，BCl 3，Br 2，HF，HCl，HBr，HI， 和NF 3，并且不留下蚀刻残留物。 可以向含卤素的气体中加入惰性气体或惰性气体和氧化剂气体。 在一个实施例中，在MOS晶体管的有源区域的部分上去除高k栅极电介质层。 或者，高k电介质层用于两个导电层之间的电容器中，并且从ILD层的部分选择性地去除。