公开(公告)号：US20160034406A1

公开(公告)日：2016-02-04

申请号：US14449689

申请日：2014-08-01

Applicant: ARM Limited

Inventor： Andreas HANSSON ,  Aniruddha Nagendran UDIPI ,  Neha AGARWAL

IPC: G06F13/18 ,  G11C7/10 ,  G06F13/16

Abstract: A memory controller and method are provided for controlling a memory device to process access requests issued by at least one master device, the memory device having a plurality of access regions. The memory controller has a pending access requests storage that buffers access requests that have been issued by a master device prior to those access requests being processed by the memory device. Access control circuitry then issues control commands to the plurality of access regions in order to control the memory device to process access requests retrieved from the pending access requests storage. A query structure is also provided that is configured to maintain, for each access region, information about the buffered access requests in the pending access requests storage, and the access control circuitry references the query structure when determining the control commands to be issued to the plurality of access regions. Such an approach enables significant performance and energy savings to be realized in control of the memory device, without requiring the contents of the pending access requests storage to be directly monitored by the access control circuitry.

Abstract translation: 提供了一种用于控制存储器设备以处理由至少一个主设备发出的访问请求的存储器控​​制器和方法，该存储器设备具有多个访问区域。 存储器控制器具有待处理的访问请求存储，其缓冲由存储设备处理的那些访问请求之前由主设备发出的访问请求。 然后，访问控制电路向多个访问区域发出控制命令，以便控制存储器设备处理从挂起的访问请求存储器检索的访问请求。 还提供了一种查询结构，其被配置为为每个访问区域维护关于未决访问请求存储器中缓冲的访问请求的信息，并且当确定要发布给多个访问请求的控制命令时，访问控制电路参考查询结构 的访问区域。 这种方法使得能够在控制存储器设备时实现显着的性能和能量节省，而不需要由访问控制电路直接监视未决访问请求存储的内容。

公开(公告)号：US20180143679A1

公开(公告)日：2018-05-24

申请号：US15566386

申请日：2016-03-10

Applicant: ARM LIMITED

Inventor： Andreas HANSSON ,  Ashley John CRAWFORD ,  Stephan DIESTELHORST ,  James Edward MYERS

IPC: G06F1/32

CPC classification number: G06F1/329 ,  G06F1/263 ,  G06F1/3228 ,  H02J7/345 ,  H02J2007/0067 ,  Y02D10/24

Abstract: There is provided an apparatus comprising a requirement determination unit to determine an energy requirement for a system component. A status determination unit determines status information relating to a plurality of heterogeneous energy stores and actuating system control unit controls an activity of the system component in dependence on the status information relating to the plurality of heterogeneous energy stores and the energy requirement.

公开(公告)号：US20180089079A1

公开(公告)日：2018-03-29

申请号：US15273743

申请日：2016-09-23

Applicant: ARM Limited

Inventor： Andreas HANSSON ,  Wendy Arnott ELSASSER ,  Michael Andrew CAMPBELL

IPC: G06F12/06 ,  G06F13/16 ,  G06F12/084 ,  G06F12/0888

CPC classification number: G06F12/0623 ,  G06F12/084 ,  G06F12/0888 ,  G06F13/1663 ,  G06F13/4234 ,  G06F2212/6046 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller is arranged to orchestrate direct data transfer by transmitting a first direct transfer command to a first memory module and a second direct transfer command to a second memory module. The first memory module is responsive to receipt of the first direct transfer command to directly transmit the data for receipt by the second memory module in a way that bypasses the memory controller. The second memory module is responsive to the second direct transfer command to receive the data from the first memory module directly, rather than requiring the data to have been routed via the memory controller, and then stores that data in dependence on the second direct transfer command. This provides an efficient mechanism for transferring data between multiple memory modules coupled to the same memory controller.

公开(公告)号：US20170185528A1

公开(公告)日：2017-06-29

申请号：US15325250

申请日：2015-06-22

Applicant: ARM LIMITED

Inventor： Andreas HANSSON ,  Ali SAIDI ,  Aniruddha Nagendran UDIPI ,  Stephan DIESTELHORST

IPC: G06F12/1036

CPC classification number: G06F12/1036 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/651 ,  G06F2212/654 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684 ,  Y02D10/13

Abstract: A data processing apparatus and method are provided for performing address translation in response to a memory access request issued by processing circuitry of the data processing apparatus and specifying a virtual address for a data item. Address translation circuitry performs an address translation process with reference to at least one descriptor provided by at least one page table, in order to produce a modified memory access request specifying a physical address for the data item. The address translation circuitry includes page table walk circuitry configured to generate at least one page table walk request in order to retrieve the at least one descriptor required for the address translation process. In addition, walk ahead circuitry is located in a path between the address translation circuitry and a memory device containing the at least one page table. The walk ahead circuitry comprises detection circuitry used to detect a memory page table walk request generated by the page table walk circuitry of the address translation circuitry for a descriptor in a page table. In addition, the walk ahead circuitry has further request generation circuitry which is used to generate a prefetch memory request in order to prefetch data from the memory device at a physical address determined with reference to the descriptor requested by the detected memory page table walk request. This prefetched data may be another descriptor required as part of the address translation process, or may be the actual data item being requested by the processing circuitry. Such an approach can significantly reduce latency associated with the address translation process.

公开(公告)号：US20160188209A1

公开(公告)日：2016-06-30

申请号：US14969414

申请日：2015-12-15

Applicant: ARM Limited

Inventor： Andreas HANSSON ,  Ian Rudolf BRATT

IPC: G06F3/06 ,  G06F12/08

Abstract: An apparatus and method are provided for issuing access requests to a memory controller for a memory device whose memory structure consists of a plurality of sub-structures. The apparatus has a request interface for issuing access requests to the memory controller, each access request identifying a memory address. Within the apparatus static abstraction data is stored providing an indication of one or more of the sub-structures of the memory device, and the apparatus also stores an indication of outstanding access requests issued from the request interface. Next access request selection circuitry is then arranged to select from a plurality of candidate access requests a next access request to issue from the request interface. That selection is dependent on sub-structure indication data that is derived from application of an abstraction data function, using the static abstraction data, to the memory addresses of the candidate access requests and the outstanding access requests. Such an approach enables the apparatus to provide a series of access requests to the memory controller with the aim of enabling the memory controller to perform a more optimal access sequence with regard to the memory device.

Abstract translation: 提供了一种用于向存储器控制器发出访问请求的装置和方法，该存储器设备的存储器结构由多个子结构组成。 该装置具有用于向存储器控制器发出访问请求的请求接口，每个访问请求标识存储器地址。 在设备内，静态抽象数据被存储，提供存储设备的一个或多个子结构的指示，并且该设备还存储从请求接口发出的未完成的访问请求的指示。 然后，下一访问请求选择电路被布置成从多个候选访问请求中选择要从请求接口发出的下一访问请求。 该选择取决于从应用抽象数据功能（使用静态抽象数据）到候选访问请求的存储器地址和未完成的访问请求导出的子结构指示数据。 这样的方法使得设备能够向存储器控制器提供一系列访问请求，目的是使得存储器控制器能够针对存储器件执行更优化的访问顺序。

公开(公告)号：US20190384718A1

公开(公告)日：2019-12-19

申请号：US16464019

申请日：2017-09-15

Applicant: ARM LIMITED

Inventor： Andreas HANSSON ,  Nikos NIKOLERIS ,  Wendy Arnott ELSASSER

IPC: G06F12/0895 ,  G06F12/0864 ,  G11C11/406 ,  G11C11/16

Abstract: Storage circuitry comprises an array of storage locations arranged in rows and columns, a row buffer comprising a plurality of entries each to store information from a storage location at a corresponding column of an active row of the array, and comparison circuitry responsive to a tag-matching command specifying a tag value to compare the tag value with information stored in each of a subset of two or more entries of the row buffer. The comparison circuitry identifies which of the subset of entries, if any, is a matching entry storing information matching the tag value. This allows memory technologies such as DRAM to be used more efficiently as a set-associative cache.

公开(公告)号：US20190163631A1

公开(公告)日：2019-05-30

申请号：US16321057

申请日：2017-06-26

Applicant: ARM LIMITED

Inventor： Andreas HANSSON

IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/0893 ,  G06F15/78 ,  G06F9/38

Abstract: A memory unit includes a data storage to store data, an operation controller to receive operation requests issued by an upstream source, a downstream capabilities storage to store an indication of operations performable by at least one downstream memory unit, and processing circuitry to perform operations on data stored in the data storage under control of the operation controller. When an operation request to perform an operation on target data is received from the upstream request source, the operation controller is arranged to determine when to control the processing circuitry to perform the operation, and when to forward the operation to a downstream memory unit in dependence on whether the target data is stored in the data storage unit and the indication of operations performable by at least one downstream memory unit. This allows for operations to be executed at a suitable location within a memory system, taking into account not only where the data resides, but also the complexity of the operation and the capabilities of the processing circuitry provided at various memory locations within the memory system.

公开(公告)号：US20180114575A1

公开(公告)日：2018-04-26

申请号：US15842207

申请日：2017-12-14

Applicant: ARM Limited

Inventor： Shidhartha DAS ,  Andreas HANSSON ,  Akshay KUMAR ,  Piyush AGARWAL ,  Azeez Jennudin BHAVNAGARWALA ,  Lucian SHIFREN

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2207/2263 ,  G11C2213/31

Abstract: A method of writing a state to a correlated electron element in a storage circuit, comprising receiving a write command to write the state into the correlated electron element; reading a stored state of the correlated electron element; comparing the state and the stored state; and enabling a write driver to write the state into the correlated electron element when the state and read state are different.

公开(公告)号：US20170371793A1

公开(公告)日：2017-12-28

申请号：US15194902

申请日：2016-06-28

Applicant: ARM Limited

Inventor： Ali SAIDI ,  Kshitij SUDAN ,  Andrew Joseph RUSHING ,  Andreas HANSSON ,  Michael FILIPPO

IPC: G06F12/0871 ,  G06F12/0873 ,  G06F12/0895

CPC classification number: G06F12/0871 ,  G06F12/0868 ,  G06F12/0873 ,  G06F12/0895 ,  G06F2212/305 ,  G06F2212/401 ,  G06F2212/466

Abstract: Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. The first and second memory regions may be located in the same row of a DRAM, for example, or in different regions of a DRAM and may be configured to enable standard DRAM components to be used. Compression and decompression logic circuits may be included in a memory controller.

公开(公告)号：US20170160933A1

公开(公告)日：2017-06-08

申请号：US15320380

申请日：2015-05-19

Applicant: ARM LIMITED

Inventor： Irenéus Johannes DE JONG ,  Andreas HANSSON

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/02 ,  G06F12/0802

CPC classification number: G06F3/061 ,  G06F3/06 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/0802 ,  G06F12/10 ,  G06F13/16 ,  G06F2212/222 ,  G06F2212/65 ,  G06F2212/7201

Abstract: A device controller and method are provided for performing a plurality of write transactions atomically within a non-volatile data storage device. Each transaction specifies a logical address and the method comprises creating an address translation map for the logical addresses specified by the plurality of write transactions, by referencing an address translation record within the non-volatile data storage device to determine for each logical address a corresponding physical address within the data storage device. Further, if the corresponding physical address indicated in the address translation record already contains valid data, the logical address is remapped to a new physical address in the address translation map. However, at this point the address translation record as stored in the data storage device is not updated. Instead, the plurality of write transactions are performed using the logical address to physical address mapping in the address translation map. Then, only once the plurality of write transactions have been performed is the address translation record updated in the non-volatile data storage device in order to identify the logical address to physical address mapping in the address translation map. Since, at the time of performing the write transactions, any new data that updates data already stored in the data storage device is written into a different physical address location, and hence the previous version of the data is still stored on the data storage device, and given that the address translation record is not updated unless the plurality of write transactions are actually performed atomically, then this enables the state held on the data storage device to be rolled back to the state that existed prior to performing the plurality of write transactions, if any event prevents that plurality of write transactions being performed atomically.