公开(公告)号：US09124292B2

公开(公告)日：2015-09-01

申请号：US14537532

申请日：2014-11-10

Applicant: ANALOG DEVICES GLOBAL

Inventor： Zhao Li ,  Shipra Bhal ,  Kevin Glenn Gard ,  David Nelson Alldred ,  Christopher Mayer ,  Trevor Clifford Caldwell ,  David J. McLaurin ,  Victor Kozlov

IPC: H03M1/10 ,  H03M3/00 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M3/384 ,  H03M1/00 ,  H03M1/1009 ,  H03M1/12 ,  H03M3/458

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract translation: 用于模数转换器（ADC）的校准系统，内部ADC接收模拟输入并将模拟输入转换为数字多位数据。 该校准系统还包括一个参考混洗电路，它洗牌内部ADC的比较器参考值。 此外，校准系统包括校准电路，校准内部ADC的比较器。 校准系统包括基于数字多位数据测量幅度的数字块。 此外，校准系统包括基于数字块的输出来控制校准电路的校准逻辑。

公开(公告)号：US10056914B2

公开(公告)日：2018-08-21

申请号：US15282586

申请日：2016-09-30

Applicant: ANALOG DEVICES GLOBAL

Inventor： Zhao Li ,  Hajime Shibata ,  Trevor Clifford Caldwell ,  Richard E. Schreier ,  Victor Kozlov ,  David Nelson Alldred ,  Prawal Man Shrestha

IPC: H03M1/10 ,  H03M1/36 ,  H03M3/00

CPC classification number: H03M1/1023 ,  H03M1/1004 ,  H03M1/1038 ,  H03M1/1085 ,  H03M1/361 ,  H03M3/378 ,  H03M3/384

Abstract: A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.

公开(公告)号：US09912342B2

公开(公告)日：2018-03-06

申请号：US15369175

申请日：2016-12-05

Applicant: Analog Devices Global

Inventor： Zhao Li ,  Hajime Shibata ,  Trevor Clifford Caldwell ,  Yunzhi Dong ,  Jialin Zhao ,  Richard E. Schreier ,  Victor Kozlov ,  David Nelson Alldred ,  Prawal Man Shrestha

IPC: H03M1/10 ,  H03M1/34 ,  H03M1/12 ,  H03M1/06 ,  H03M3/00

CPC classification number: H03M1/1009 ,  H03M1/0626 ,  H03M1/066 ,  H03M1/1245 ,  H03M1/34 ,  H03M3/388 ,  H03M3/422

Abstract: An analog-to-digital converter (ADC) is a device that can include a reference shuffler and a loop filter. An ADC can achieve better performance with incremental adjustment of a pointer of the reference shuffler, changing coefficients of the loop filter, and storing calibration codes of the ADC in a non-volatile memory. By incrementally adjusting a pointer of the reference shuffler, a calibration can be performed more efficiently than with a random adjustment of the pointer. By temporarily changing the loop filter coefficients, a greater amount of activity can be introduced into the loop filter. This activity can allow the calibration to proceed more efficiently. By storing the calibration codes in a non-volatile memory, a search space for calibration codes can be reduced. Thus, a calibration can occur more quickly, and the calibration itself can be improved.

公开(公告)号：US09838031B2

公开(公告)日：2017-12-05

申请号：US15360984

申请日：2016-11-23

Applicant: Analog Devices Global

Inventor： Yunzhi Dong ,  Hajime Shibata ,  Trevor Clifford Caldwell ,  Zhao Li ,  Jialin Zhao ,  Jose Barreiro Silva

IPC: H03M3/00 ,  H03M1/36

CPC classification number: H03M3/422 ,  H03M1/361 ,  H03M3/322 ,  H03M3/344 ,  H03M3/378 ,  H03M3/388 ,  H03M3/414 ,  H03M3/436 ,  H03M3/464

Abstract: For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.

公开(公告)号：US10171102B1

公开(公告)日：2019-01-01

申请号：US15865742

申请日：2018-01-09

Applicant: Analog Devices Global Unlimited Company

Inventor： Hajime Shibata ,  Yunzhi Dong ,  Zhao Li ,  Trevor Clifford Caldwell ,  Wenhua William Yang

IPC: H03M1/12 ,  H03M3/00 ,  H03M1/66 ,  H03M1/06

Abstract: A linear continuous-time (CT) delaying summation block is one of the key building blocks for CT multi-stage analog-to-digital converters (ADCs) such as CT pipeline ADCs and CT multi-stage delta-sigma (MASH) ADCs. The CT summation block is typically used on a stage of a CT multi-stage ADC to subtract a digital-to-analog converter (DAC) output signal from an analog input signal of the stage. Rather than using a current-mode summation, the CT delaying summation block can be implemented with voltage-mode summation.

公开(公告)号：US09843337B1

公开(公告)日：2017-12-12

申请号：US15460433

申请日：2017-03-16

Applicant: Analog Devices Global

Inventor： Zhao Li ,  Trevor Clifford Caldwell ,  David Nelson Alldred ,  Yunzhi Dong ,  Prawal Man Shrestha ,  Jialin Zhao ,  Hajime Shibata ,  Victor Kozlov ,  Richard E. Schreier ,  Wenhua W. Yang

IPC: H03M1/12 ,  H03M1/10 ,  H03M3/00

CPC classification number: H03M1/1023 ,  H03M1/0673 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/361 ,  H03M3/384 ,  H03M3/414

Abstract: Analog-to-digital converters (ADCs) can be used inside ADC architectures, such as delta-sigma ADCs. The error in such internal ADCs can degrade performance. To calibrate the errors in an internal ADC, comparator offsets of the internal ADC can be estimated by computing a mean of each comparator of the internal ADC. Relative differences in the computed means serves as estimates for comparator offsets. If signal paths in the internal ADC are shuffled, the estimation of comparator offsets can be performed in the background without interrupting normal operation. Shuffling of signal paths may introduce systematic measurement errors, which can be measured and reversed to improve the estimation of comparator offsets.

公开(公告)号：US09762221B2

公开(公告)日：2017-09-12

申请号：US15182430

申请日：2016-06-14

Applicant: ANALOG DEVICES GLOBAL

Inventor： Yunzhi Dong ,  Victor Kozlov ,  Wenhua W. Yang ,  Trevor Clifford Caldwell ,  Hajime Shibata

IPC: H03M1/38 ,  H03K5/14 ,  H03M1/00 ,  H03M3/00 ,  H03H7/30 ,  H03K5/00

CPC classification number: H03K5/14 ,  H03H7/30 ,  H03K2005/00254 ,  H03K2005/00267 ,  H03M1/001 ,  H03M1/164 ,  H03M3/464

Abstract: An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.

公开(公告)号：US10608851B2

公开(公告)日：2020-03-31

申请号：US15896355

申请日：2018-02-14

Applicant: Analog Devices Global Unlimited Company

Inventor： Hajime Shibata ,  Brian Holford ,  Trevor Clifford Caldwell ,  Siddharth Devarajan

IPC: H03M1/12 ,  H04L25/06 ,  H04L12/26 ,  H04L27/156 ,  G11C27/02 ,  G11C7/22 ,  G01R13/34

Abstract: A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively “holds” or provides the input signal value at the output for further processing without requiring switched-capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the front end sampler in a variety of analog-to-digital converters.

公开(公告)号：US20190253286A1

公开(公告)日：2019-08-15

申请号：US15896355

申请日：2018-02-14

Applicant: Analog Devices Global Unlimited Company

Inventor： Hajime Shibata ,  Brian Holford ,  Trevor Clifford Caldwell ,  Siddharth Devarajan

IPC: H04L25/06 ,  H03M1/12 ,  H04L27/156 ,  H04L12/26

CPC classification number: H04L25/069 ,  G01R13/34 ,  G11C27/02 ,  H03M1/1245 ,  H03M1/1255 ,  H04L27/1563 ,  H04L43/0852

Abstract: A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively “holds” or provides the input signal value at the output for further processing without requiring switched-capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the front end sampler in a variety of analog-to-digital converters.

公开(公告)号：US09350371B2

公开(公告)日：2016-05-24

申请号：US14571274

申请日：2014-12-15

Applicant: ANALOG DEVICES GLOBAL

Inventor： Trevor Clifford Caldwell ,  Richard E. Schreier ,  David Alldred ,  Wenhua W. Yang

IPC: H03M3/00 ,  H03M1/06 ,  H03M1/36 ,  H03M1/74

CPC classification number: H03M1/0673 ,  H03M1/361 ,  H03M1/74 ,  H03M3/30 ,  H03M3/338 ,  H03M3/464

Abstract: In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.

Abstract translation: 一方面，公开了一种电信号转换器。 示例性电信号转换器可以包括多个有序的转换器元件。 可以提供元素选择逻辑以伪随机选择指向开关矩阵的指针，其中开关矩阵根据逐步的“二进制二最大模式”来映射转换器元件。有利地，可以应用伪随机逐步的Δ-二最大模式 到一阶转换器和用于纠错的反馈转换器。