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    Stacked chip security
    1.
    发明授权
    Stacked chip security 有权
    堆叠芯片安全

    公开(公告)号：US07557597B2

    公开(公告)日：2009-07-07

    申请号：US11145423

    申请日：2005-06-03

    Applicant: Brent Alan Anderson ,  Edmund Juris Sprogis

    Inventor： Brent Alan Anderson ,  Edmund Juris Sprogis

    IPC: G01R31/02

    CPC classification number: H01L23/585 ,  H01L23/576 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/48227 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: The present invention is directed to an integrated circuit module device. The device includes a first semiconductor chip having a first circuit layer and at least one first interconnection element disposed on a first chip surface. The at least one first interconnection element is electrically coupled to the first circuit layer. A second semiconductor chip includes a second circuit layer and at least one second interconnection element disposed on a second chip surface. The at least one second interconnection element is electrically coupled to the second circuit layer. The at least one first interconnection element is connected to the at least one second interconnection element to establish electrical continuity between the first circuit layer and the second circuit layer. The first surface is adjoined to the second surface. At least one ring delay circuit includes a first ring delay path partially disposed on the first circuit layer and a second ring delay path partially disposed on the second circuit layer. The first ring delay path and the second ring delay path form a signal path having a predetermined measurement signature. The ring delay circuit compares the predetermined measurement signature to a test measurement signature.

    Abstract translation: 本发明涉及一种集成电路模块装置。 该器件包括具有第一电路层的第一半导体芯片和设置在第一芯片表面上的至少一个第一互连元件。 所述至少一个第一互连元件电耦合到所述第一电路层。 第二半导体芯片包括第二电路层和设置在第二芯片表面上的至少一个第二互连元件。 所述至少一个第二互连元件电耦合到第二电路层。 所述至少一个第一互连元件连接到所述至少一个第二互连元件，以在所述第一电路层和所述第二电路层之间建立电连续性。 第一表面与第二表面相邻。 至少一个环形延迟电路包括部分地设置在第一电路层上的第一环延迟路径和部分地设置在第二电路层上的第二环延迟路径。 第一环延迟路径和第二环延迟路径形成具有预定测量签名的信号路径。 环形延迟电路将预定测量签名与测试测量签名进行比较。

    Method of making through wafer vias
    2.
    发明授权
    Method of making through wafer vias 有权
    通过晶片通孔制作方法

    公开(公告)号：US07678696B2

    公开(公告)日：2010-03-16

    申请号：US12188230

    申请日：2008-08-08

    Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

    Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

    IPC: H01L21/44

    CPC classification number: H01L21/76898

    Abstract: A method of making a through wafer via. The method includes: forming a trench in a semiconductor substrate, the trench open to a top surface of the substrate; forming a polysilicon layer on sidewalls and a bottom of the trench; oxidizing the polysilicon layer to convert the polysilicon layer to a silicon oxide layer on the sidewalls and bottom of the trench, the silicon oxide layer not filling the trench; filling remaining space in the trench with an electrical conductor; and thinning the substrate from a bottom surface of the substrate and removing the silicon oxide layer from the bottom of the trench. The method may further include forming a metal layer on the silicon oxide layer before filling the trench.

    Abstract translation: 制造通过晶片通孔的方法。 该方法包括：在半导体衬底中形成沟槽，沟槽通向衬底的顶表面; 在沟槽的侧壁和底部上形成多晶硅层; 氧化多晶硅层以将多晶硅层转变成沟槽的侧壁和底部上的氧化硅层，氧化硅层不填充沟槽; 用电导体填充沟槽中的剩余空间; 以及从衬底的底表面使衬底细化并从沟槽的底部去除氧化硅层。 该方法还可以包括在填充沟槽之前在氧化硅层上形成金属层。

    PHOTOLITHOGRAPHY MASK WITH PROTECTIVE CAPPING LAYER
    3.
    发明申请
    PHOTOLITHOGRAPHY MASK WITH PROTECTIVE CAPPING LAYER 审中-公开
    具有保护层的光刻胶面

    公开(公告)号：US20080261122A1

    公开(公告)日：2008-10-23

    申请号：US11738070

    申请日：2007-04-20

    Applicant: Jeffrey Peter Gambino ,  Robert Kenneth Leidy ,  Kirk David Peterson ,  Jed Hickory Rankin ,  Edmund Juris Sprogis

    Inventor： Jeffrey Peter Gambino ,  Robert Kenneth Leidy ,  Kirk David Peterson ,  Jed Hickory Rankin ,  Edmund Juris Sprogis

    IPC: G03C5/00 ,  G03F1/00

    CPC classification number: G03F1/30 ,  G03F1/48 ,  G03F1/54

    Abstract: A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and a top surface; the non-printable region comprising a second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and a top surface; and a capping layer on the sidewalls of the first opaque regions and the sidewalls of the second opaque region.

    Abstract translation: 光掩模和制造光掩模的方法。 所述光掩模包括：对所选择的波长或辐射波长透明的衬底，所述衬底具有顶表面和相对的底表面，所述衬底具有可打印区域和不可打印区域; 所述可印刷区域具有在所述基板的与所述透明区域相邻的顶表面上方的第一不透明区域，所述第一不透明区域的每个不透明区域具有侧壁和顶表面; 所述不可打印区域包括在所述基板的顶表面上方升高的第二不透明区域，所述第二不透明区域具有侧壁和顶表面; 以及在第一不透明区域的侧壁和第二不透明区域的侧壁上的覆盖层。

    METHOD OF MAKING THROUGH WAFER VIAS
    6.
    发明申请
    METHOD OF MAKING THROUGH WAFER VIAS 有权
    通过WAVER VIAS制作的方法

    公开(公告)号：US20100035430A1

    公开(公告)日：2010-02-11

    申请号：US12188230

    申请日：2008-08-08

    Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

    Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

    IPC: H01L21/768

    CPC classification number: H01L21/76898

    Abstract: A method of making a through wafer via. The method includes: forming a trench in a semiconductor substrate, the trench open to a top surface of the substrate; forming a polysilicon layer on sidewalls and a bottom of the trench; oxidizing the polysilicon layer to convert the polysilicon layer to a silicon oxide layer on the sidewalls and bottom of the trench, the silicon oxide layer not filling the trench; filling remaining space in the trench with an electrical conductor; and thinning the substrate from a bottom surface of the substrate and removing the silicon oxide layer from the bottom of the trench. The method may further include forming a metal layer on the silicon oxide layer before filling the trench.

    Abstract translation: 制造通过晶片通孔的方法。 该方法包括：在半导体衬底中形成沟槽，沟槽通向衬底的顶表面; 在沟槽的侧壁和底部上形成多晶硅层; 氧化多晶硅层以将多晶硅层转变成沟槽的侧壁和底部上的氧化硅层，氧化硅层不填充沟槽; 用电导体填充沟槽中的剩余空间; 以及从衬底的底表面使衬底细化并从沟槽的底部去除氧化硅层。 该方法还可以包括在填充沟槽之前在氧化硅层上形成金属层。

    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME
    7.
    发明申请
    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 有权
    通过VIAS的低电阻和电感及其制造方法

    公开(公告)号：US20090184423A1

    公开(公告)日：2009-07-23

    申请号：US12410728

    申请日：2009-03-25

    Applicant: Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

    Inventor： Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

    IPC: H01L23/48 ,  H01L21/30

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

    Abstract translation: 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

    Through-wafer vias
    9.
    发明授权
    Through-wafer vias 有权
    通晶圆通孔

    公开(公告)号：US07741722B2

    公开(公告)日：2010-06-22

    申请号：US11690181

    申请日：2007-03-23

    Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

    Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

    IPC: H01L23/48

    CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    Abstract: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

    Abstract translation: 一种晶片通孔结构及其形成方法。 贯通晶片通孔结构包括具有开口和顶部晶片表面的晶片。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 贯通晶片通孔结构还包括在开口中的通晶片通孔。 贯通晶片通孔具有矩形板的形状。 贯通晶片通孔在第一参考方向上的高度基本上等于晶片在第一参考方向上的厚度。 贯穿晶片通孔在第二参考方向上的长度比通过晶片通孔在第三参考方向上的宽度大至少十倍。 第一，第二和第三参考方向彼此垂直。

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