公开(公告)号：US20210384406A1

公开(公告)日：2021-12-09

申请号：US17321819

申请日：2021-05-17

Applicant: D-WAVE SYSTEMS INC.

Inventor： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC: H01L39/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/18 ,  H01L39/12

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

公开(公告)号：US20240138268A1

公开(公告)日：2024-04-25

申请号：US18277688

申请日：2022-02-17

Applicant: D-WAVE SYSTEMS INC.

Inventor： Colin C. Enderud ,  Mohammad H. Amin ,  Loren J. Swenson

IPC: H10N60/01 ,  H01L23/522 ,  H01L23/532 ,  H01L25/18 ,  H10N60/12 ,  H10N60/80 ,  H10N69/00

CPC classification number: H10N60/0912 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/53285 ,  H01L25/18 ,  H10N60/12 ,  H10N60/805 ,  H10N69/00

Abstract: A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material. A superconducting integrated circuit has a first stack with a first superconducting wiring layer formed from a first high kinetic inductance material and a second superconducting wiring layer communicatively coupled to the first superconducting wiring layer to form a first control circuit, a second stack comprising a third superconducting wiring layer formed from a second high kinetic inductance material and a fourth superconducting wiring layer communicatively coupled the third superconducting wiring layer to form a second control circuit. The superconducting integrated circuit also has a third stack with a controllable device, and at least one of the first control circuit and the second control circuit is communicatively coupled to the controllable device.

公开(公告)号：US20170178018A1

公开(公告)日：2017-06-22

申请号：US15382278

申请日：2016-12-16

Applicant: D-Wave Systems Inc.

Inventor： Alexandr M. Tcaciuc ,  Pedro A. de Buen ,  Peter D. Spear ,  Sergey V. Uchaykin ,  Colin C. Enderud ,  Richard D. Neufeld ,  Jeremy P. Hilton ,  J. Craig Petroff ,  Amar B. Kamdar ,  Gregory D. Peregrym ,  Edmond Ho Yin Kan ,  Loren J. Swenson ,  George E.G. Sterling ,  Gregory Citver

IPC: G06N99/00 ,  H01L39/12 ,  H01L39/24 ,  H05K3/34 ,  H05K9/00 ,  F25B43/00 ,  H01L39/18 ,  H01F41/06 ,  H01F41/04 ,  H01F13/00 ,  F25B9/12 ,  H03H3/00 ,  H05K1/02

CPC classification number: G06N10/00 ,  H01F13/006 ,  H01F41/048 ,  H01F41/076 ,  H01L39/02 ,  H01L39/14 ,  H03H3/00 ,  H03H7/425 ,  H03H2001/005 ,  H05K1/0233 ,  H05K1/0245 ,  H05K1/16 ,  H05K2201/10287

Abstract: An electrical filter includes a dielectric substrate with inner and outer coils about a first region and inner and outer coils about a second region, a portion of cladding removed from wires that form the coils and coupled to electrically conductive traces on the dielectric substrate via a solder joint in a switching region. An apparatus to thermally couple a superconductive device to a metal carrier with a through-hole includes a first clamp and a vacuum pump. A composite magnetic shield for use at superconductive temperatures includes an inner layer with magnetic permeability of at least 50,000; and an outer layer with magnetic saturation field greater than 1.2 T, separated from the inner layer by an intermediate layer of dielectric. An apparatus to dissipate heat from a superconducting processor includes a metal carrier with a recess, a post that extends upwards from a base of the recess and a layer of adhesive on top of the post. Various cryogenic refrigeration systems are described.

公开(公告)号：US20250040454A1

公开(公告)日：2025-01-30

申请号：US18790374

申请日：2024-07-31

Applicant: D-WAVE SYSTEMS INC.

Inventor： Loren J. Swenson ,  George E.G. Sterling ,  Mark H. Volkmann ,  Colin C. Enderud

IPC: H10N69/00 ,  G06N10/40 ,  H10N60/12 ,  H10N60/80

Abstract: A circuit can include a galvanic coupling of a coupler to a qubit by a segment of kinetic inductance material. The circuit can include a galvanic kinetic inductance coupler having multiple windings. The circuit can include a partially-galvanic coupler having multiple windings. The partially-galvanic coupler can include a magnetic coupling and a galvanic coupling. The circuit can include an asymmetric partially-galvanic coupler having a galvanic coupling and a first magnetic coupling to one qubit and a second magnetic coupling to a second qubit. The circuit can include a compact kinetic inductance qubit having a qubit body loop comprising a kinetic inductance material. A multilayer integrated circuit including a kinetic inductance layer can form a galvanic kinetic inductance coupling. A multilayer integrated circuit including a kinetic inductance layer can form at least a portion of a compact kinetic inductance qubit body loop.

公开(公告)号：US11957065B2

公开(公告)日：2024-04-09

申请号：US17321819

申请日：2021-05-17

Applicant: D-WAVE SYSTEMS INC.

Inventor： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC: H10N60/01 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10N60/85 ,  H10N69/00

CPC classification number: H10N60/0156 ,  H01L21/76891 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53285 ,  H10N60/85 ,  H10N69/00

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

公开(公告)号：US11038095B2

公开(公告)日：2021-06-15

申请号：US16481788

申请日：2018-01-31

Applicant: D-WAVE SYSTEMS INC.

Inventor： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC: H01L27/18 ,  H01L39/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L39/12

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

公开(公告)号：US12102017B2

公开(公告)日：2024-09-24

申请号：US17429456

申请日：2020-02-13

Applicant: D-WAVE SYSTEMS INC.

Inventor： Loren J. Swenson ,  George E. G. Sterling ,  Mark H. Volkmann ,  Colin C. Enderud

IPC: H10N69/00 ,  G06N10/40 ,  H10N60/12 ,  H10N60/80

CPC classification number: H10N69/00 ,  G06N10/40 ,  H10N60/12 ,  H10N60/805

Abstract: A circuit can include a galvanic coupling of a coupler to a qubit by a segment of kinetic inductance material. The circuit can include a galvanic kinetic inductance coupler having multiple windings. The circuit can include a partially-galvanic coupler having multiple windings. The partially-galvanic coupler can include a magnetic coupling and a galvanic coupling. The circuit can include an asymmetric partially-galvanic coupler having a galvanic coupling and a first magnetic coupling to one qubit and a second magnetic coupling to a second qubit. The circuit can include a compact kinetic inductance qubit having a qubit body loop comprising a kinetic inductance material. A multilayer integrated circuit including a kinetic inductance layer can form a galvanic kinetic inductance coupling. A multilayer integrated circuit including a kinetic inductance layer can form at least a portion of a compact kinetic inductance qubit body loop.

公开(公告)号：US20240237555A9

公开(公告)日：2024-07-11

申请号：US18277688

申请日：2022-02-17

Applicant: D-WAVE SYSTEMS INC.

Inventor： Colin C. Enderud ,  Mohammad H. Amin ,  Loren J. Swenson

IPC: H10N60/01 ,  H01L23/522 ,  H01L23/532 ,  H01L25/18 ,  H10N60/12 ,  H10N60/80 ,  H10N69/00

CPC classification number: H10N60/0912 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/53285 ,  H01L25/18 ,  H10N60/12 ,  H10N60/805 ,  H10N69/00

Abstract: A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material. A superconducting integrated circuit has a first stack with a first superconducting wiring layer formed from a first high kinetic inductance material and a second superconducting wiring layer communicatively coupled to the first superconducting wiring layer to form a first control circuit, a second stack comprising a third superconducting wiring layer formed from a second high kinetic inductance material and a fourth superconducting wiring layer communicatively coupled the third superconducting wiring layer to form a second control circuit. The superconducting integrated circuit also has a third stack with a controllable device, and at least one of the first control circuit and the second control circuit is communicatively coupled to the controllable device.

公开(公告)号：US20240070510A1

公开(公告)日：2024-02-29

申请号：US18272235

申请日：2022-01-11

Applicant: D-WAVE SYSTEMS INC.

Inventor： Min Jan Tsai ,  Colin C. Enderud ,  Reza Molavi ,  Paul I. Bunyk

IPC: G06N10/40 ,  H03M1/66

CPC classification number: G06N10/40 ,  H03M1/66

Abstract: Programmable components of a quantum processor may be selectively programmed using digital to analog converters (DACs). A DAC with a first stage and a second stage and first and second quantum flux parametron (OFF) loops galvanically coupled to and extending from a respective one of the first stage and the second stage is discussed. The first stage has a first storage loop interrupted by a first Josephson junction and an interface for communicating with an external component. The second stage has a second storage loop interrupted by a second Josephson junction, the second storage loop galvanically coupled to the first storage loop, the first Josephson junction and the second Josephson junction coupled in series to a first control line. A method of loading flux quanta into targeted DAC stages is also discussed.

公开(公告)号：US20220123048A1

公开(公告)日：2022-04-21

申请号：US17429456

申请日：2020-02-13

Applicant: D-WAVE SYSTEMS INC.

Inventor： Loren J. Swenson ,  George E.G. Sterling ,  Mark H. Volkmann ,  Colin C. Enderud

IPC: H01L27/18 ,  H01L39/02 ,  H01L39/22 ,  G06N10/40

Abstract: A circuit can include a galvanic coupling of a coupler to a qubit by a segment of kinetic inductance material. The circuit can include a galvanic kinetic inductance coupler having multiple windings. The circuit can include a partially-galvanic coupler having multiple windings. The partially-galvanic coupler can include a magnetic coupling and a galvanic coupling. The circuit can include an asymmetric partially-galvanic coupler having a galvanic coupling and a first magnetic coupling to one qubit and a second magnetic coupling to a second qubit. The circuit can include a compact kinetic inductance qubit having a qubit body loop comprising a kinetic inductance material. A multilayer integrated circuit including a kinetic inductance layer can form a galvanic kinetic inductance coupling. A multilayer integrated circuit including a kinetic inductance layer can form at least a portion of a compact kinetic inductance qubit body loop.