中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.014 seconds)

    Devices and methods of forming SADP on SRAM and SAQP on logic
    2.
    发明授权
    Devices and methods of forming SADP on SRAM and SAQP on logic 有权

    公开(公告)号：US09761452B1

    公开(公告)日：2017-09-12

    申请号：US15205528

    申请日：2016-07-08

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jiehui Shu ,  Daniel Jaeger ,  Garo Jacques Derderian ,  Haifeng Sheng ,  Jinping Liu

    IPC: H01L21/311 ,  H01L21/033 ,  H01L27/11

    CPC classification number: H01L27/1116 ,  H01L21/3086 ,  H01L27/1104 ,  H01L28/00

    Abstract: Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.

    FIN CUTTING PROCESS FOR MANUFACTURING FINFET SEMICONDUCTOR DEVICES
    3.
    发明申请
    FIN CUTTING PROCESS FOR MANUFACTURING FINFET SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20170250088A1

    公开(公告)日：2017-08-31

    申请号：US15056513

    申请日：2016-02-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Garo Jacques Derderian

    IPC: H01L21/306 ,  H01L21/308

    CPC classification number: H01L21/3085 ,  H01L21/3086

    Abstract: One illustrative method disclosed herein includes, among other things, forming an original fin-formation etch mask comprised of a plurality of original line-type features and removing at least a portion of at least one of the plurality of original line-type features so as to thereby define a modified fin-formation etch mask comprising the remaining portions of the plurality of original line-type features. The method also includes forming a conformal layer of material on the remaining portions of the plurality of original line-type features of the modified fin-formation etch mask and performing at least one etching process to remove at least portions of the conformal layer of material and to define a plurality of fin-formation trenches so as to thereby initially define a plurality of fins in the substrate.

    Formation of carbon-rich contact liner material
    4.
    发明授权
    Formation of carbon-rich contact liner material 有权
    富含碳的接触衬里材料的形成

    公开(公告)号：US09130019B2

    公开(公告)日：2015-09-08

    申请号：US14150260

    申请日：2014-01-08

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Huy Cao ,  Songkram Srivathanakul ,  Huang Liu ,  Garo Jacques Derderian ,  Boaz Alperson

    IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/482

    CPC classification number: H01L23/5329 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material including a carbon-containing species and an elemental carbon disposed therein, the carbon-containing species and the elemental carbon together defining a set carbon content within the carbon-rich contact liner material; and depositing the carbon-rich contact liner material conformally within the at least one contact opening disposed over the semiconductor substrate.

    Abstract translation: 提供电路结构的导电接触结构及其制造方法。 该制造包括例如提供设置在半导体衬底上的至少一个接触开口; 形成包含含碳物质和设置在其中的元素碳的富碳接触衬垫材料，所述含碳物质和所述元素碳一起限定所述富碳接触衬里材料内的固定碳含量; 以及将所述富碳接触衬垫材料共形地沉积在设置在所述半导体衬底上的所述至少一个接触开口内。

    Methods of forming reduced thickness spacers in CMOS based integrated circuit products
    6.
    发明授权
    Methods of forming reduced thickness spacers in CMOS based integrated circuit products 有权
    在基于CMOS的集成电路产品中形成厚度减薄的方法

    公开(公告)号：US09385124B1

    公开(公告)日：2016-07-05

    申请号：US14845499

    申请日：2015-09-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Wen Pin Peng ,  Min-hwa Chi ,  Garo Jacques Derderian

    IPC: H01L21/336 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165

    CPC classification number: H01L27/092 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

    Abstract: One method disclosed herein includes, among other things, forming a first spacer proximate gate structures of first and second transistors that are opposite type transistors, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, performing a timed, wet etching process on both of the transistors so as to completely remove the layer of second spacer material from the second transistor while leaving a reduced thickness second spacer positioned adjacent the first spacer of the first transistor, wherein the reduced thickness second spacer has a thickness that is less than an initial thickness of the initial second spacer, and forming a third spacer on and in contact with the first spacer of the second transistor.

    Abstract translation: 本文公开的一种方法包括形成与第一和第二晶体管相对的第一和第二晶体管的栅极结构的第一间隔区，与第一晶体管相反，形成靠近第一晶体管的第一间隔物的初始第二间隔区， 第二晶体管，对两个晶体管执行定时湿式蚀刻处理，以便从第二晶体管完全去除第二间隔物材料层，同时留下邻近第一晶体管的第一间隔物定位的减小厚度的第二间隔物，其中减少 厚度第二间隔物的厚度小于初始第二间隔物的初始厚度，并且在第二晶体管的第一间隔物上形成第三间隔物并与第二间隔物接触。

    Fin cutting process for manufacturing FinFET semiconductor devices
    8.
    发明授权
    Fin cutting process for manufacturing FinFET semiconductor devices 有权

    公开(公告)号：US09754792B1

    公开(公告)日：2017-09-05

    申请号：US15056513

    申请日：2016-02-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Garo Jacques Derderian

    IPC: H01L21/306 ,  H01L21/308

    CPC classification number: H01L21/3085 ,  H01L21/3086

    Abstract: One illustrative method disclosed herein includes, among other things, forming an original fin-formation etch mask comprised of a plurality of original line-type features and removing at least a portion of at least one of the plurality of original line-type features so as to thereby define a modified fin-formation etch mask comprising the remaining portions of the plurality of original line-type features. The method also includes forming a conformal layer of material on the remaining portions of the plurality of original line-type features of the modified fin-formation etch mask and performing at least one etching process to remove at least portions of the conformal layer of material and to define a plurality of fin-formation trenches so as to thereby initially define a plurality of fins in the substrate.

    Tapered fin-type field-effect transistors
    10.
    发明授权
    Tapered fin-type field-effect transistors 有权

    公开(公告)号：US10832967B2

    公开(公告)日：2020-11-10

    申请号：US16101963

    申请日：2018-08-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hui Zang ,  Ruilong Xie ,  Garo Jacques Derderian

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

    Abstract: Device structures and fabrication methods for a field-effect transistor. A semiconductor fin includes a first section and a second section in a lengthwise arrangement, a first gate structure overlapping the first section of the semiconductor fin, and a second gate structure overlapping the second section of the semiconductor fin. A pillar is arranged in the first section of the semiconductor fin. The pillar extends through a height of the semiconductor fin and across a width of the semiconductor fin.

Patent Agency Ranking