公开(公告)号：US10163697B2

公开(公告)日：2018-12-25

申请号：US15478385

申请日：2017-04-04

Applicant: GlobalFoundries Inc.

Inventor： Felix P. Anderson ,  Edward C. Cooney, III ,  Michael S. Dusablon ,  David C. Mosher

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02

Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.

公开(公告)号：US10224276B2

公开(公告)日：2019-03-05

申请号：US15787146

申请日：2017-10-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Robert K. Leidy

IPC: H01L29/40 ,  H01L23/522 ,  H01L23/525 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31

Abstract: Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

公开(公告)号：US20170323855A1

公开(公告)日：2017-11-09

申请号：US15594059

申请日：2017-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Edward C. Cooney, III ,  Laurie M. Krywanczyk

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/268 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76819 ,  H01L23/585 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/54493

Abstract: Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.

公开(公告)号：US09728509B1

公开(公告)日：2017-08-08

申请号：US15147525

申请日：2016-05-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Edward C. Cooney, III ,  Laurie M. Krywanczyk

IPC: H01L23/544 ,  H01L23/528 ,  H01L23/58 ,  H01L21/768 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/304 ,  H01L23/532

CPC classification number: H01L23/544 ,  H01L21/268 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/768 ,  H01L23/585 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/54493

Abstract: Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.

公开(公告)号：US10056306B2

公开(公告)日：2018-08-21

申请号：US15015478

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Gary L. Milo ,  Thomas W. Weeks ,  Patrick S. Spinney ,  John C. Hall ,  Brian P. Conchieri ,  Brett T. Cucci ,  Thomas C. Lee

IPC: H01L21/66 ,  H01L23/544 ,  G01R31/28

CPC classification number: H01L22/32 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/544

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

公开(公告)号：US09673091B2

公开(公告)日：2017-06-06

申请号：US14749817

申请日：2015-06-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Felix P. Anderson ,  Edward C. Cooney, III ,  Michael S. Dusablon ,  David C. Mosher

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/02164 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76886 ,  H01L23/53238

Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.

公开(公告)号：US09577023B2

公开(公告)日：2017-02-21

申请号：US13909464

申请日：2013-06-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Dinh Dang ,  David A. DeMuynck ,  Sarah A. McTaggart ,  Gary L. Milo ,  Melissa J. Roma ,  Jeffrey L. Thompson ,  Thomas W. Weeks

IPC: H01F5/00 ,  H01L21/00 ,  H01L21/44 ,  H01L21/4763 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.

Abstract translation: 一种包括在第一电介质层中形成第一金属线的方法，所述第一金属线包括与第二垂直侧相对的第一垂直侧; 以及在所述第一电介质层上方的第二电介质层中形成第二金属线，所述第二金属线包括与第四垂直侧相反的第三垂直侧，其中所述第一垂直侧从所述第三垂直侧横向偏移第一预定 距离，第二垂直侧从第四垂直侧横向偏移第二预定距离，其中第一金属线和第二金属线彼此直接接触。

公开(公告)号：US20180040556A1

公开(公告)日：2018-02-08

申请号：US15787146

申请日：2017-10-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Robert K. Leidy

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

公开(公告)号：US20170229358A1

公开(公告)日：2017-08-10

申请号：US15015478

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Gary L. Milo ,  Thomas W. Weeks ,  Patrick S. Spinney ,  John C. Hall ,  Brian P. Conchieri ,  Brett T. Cucci ,  Thomas C. Lee

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/544

CPC classification number: H01L22/32 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/544

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

公开(公告)号：US20170207121A1

公开(公告)日：2017-07-20

申请号：US15478385

申请日：2017-04-04

Applicant: GlobalFoundries Inc.

Inventor： Felix P. Anderson ,  Edward C. Cooney, III ,  Michael S. Dusablon ,  David C. Mosher

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/02164 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76886 ,  H01L23/53238

Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.