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    VIA LEAKAGE AND BREAKDOWN TESTING
    1.
    发明申请
    VIA LEAKAGE AND BREAKDOWN TESTING 有权
    通过泄漏和断路器测试

    公开(公告)号：US20160291084A1

    公开(公告)日：2016-10-06

    申请号：US14673185

    申请日：2015-03-30

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Fen Chen ,  Roger A. Dufresne ,  Charles W. Griffin ,  Kevin W. Kolvenbach

    IPC: G01R31/28 ,  H01L23/522

    CPC classification number: G01R31/2884 ,  G01R31/2831 ,  G01R31/2886 ,  H01L23/5226

    Abstract: Various particular embodiments include a via testing structure, including: a first terminal coupled to a first set of sensing lines in a top level of the structure; a second terminal coupled to a second set of sensing lines in the top level of the structure, wherein first set of sensing lines and the second set of sensing lines are disposed in a comb arrangement; a third terminal coupled to a third set of sensing lines in a bottom level of the structure; and a plurality of vias electrically coupling the second set of sensing lines in the top level of the structure to the third set of sensing lines in the bottom level of the structure, each via having a via top and a via bottom.

    Abstract translation: 各种特定实施例包括通孔测试结构，包括：耦合到该结构顶层中的第一组感测线的第一端子; 第二终端，其耦合到所述结构的顶层中的第二组感测线，其中第一组感测线和所述第二组感测线设置在梳状布置中; 耦合到所述结构的底层中的第三组感测线的第三端子; 以及多个通孔将结构的顶层中的第二组感测线电耦合到结构的底部水平面中的第三组感测线，每个通孔具有通孔顶部和通孔底部。

    ELECTROMIGRATION TESTING OF INTERCONNECT ANALOGUES HAVING BOTTOM-CONNECTED SENSORY PINS
    2.
    发明申请
    ELECTROMIGRATION TESTING OF INTERCONNECT ANALOGUES HAVING BOTTOM-CONNECTED SENSORY PINS 有权
    具有底部连接感应引线的互连模拟电路的电气测试

    公开(公告)号：US20160258998A1

    公开(公告)日：2016-09-08

    申请号：US14635125

    申请日：2015-03-02

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Fen Chen ,  Cathryn J. Christiansen ,  Deborah M. Massey ,  Prakash Periasamy ,  Michael A. Shinosky

    IPC: G01R31/28

    CPC classification number: G01R31/2858 ,  G01N1/00 ,  H01L21/00 ,  H01L2221/00

    Abstract: A system for electromigration testing is disclosed. The system includes a conductive member, a cap layer of insulative material over at least a portion of a top surface of the conductive member, a cathode conductively connected to a first end of the conductive member; an anode conductively connected to a second end of the conductive member, and a current source conductively connected to the cathode and the anode. A plurality of sensory pins are disposed along a length of the conductive member between the first end and the second end of the conductive member. The sensory pins are conductively connected to a bottom surface of the conductive member. At least one measurement device is conductively connected to at least one sensory pin of the plurality of sensory pins. The at least one measurement device determines a resistance of at least one portion of the conductive member.

    Abstract translation: 公开了用于电迁移测试的系统。 该系统包括导电构件，在导电构件的顶表面的至少一部分上的绝缘材料的覆盖层，阴极，导电地连接到导电构件的第一端; 导电性地连接到导电构件的第二端的阳极和与阴极和阳极导通地连接的电流源。 沿着导电构件的长度在导电构件的第一端和第二端之间设置多个感应针。 传感针与导电构件的底面导电连接。 至少一个测量装置导电地连接到多个感觉针的至少一个感觉针。 所述至少一个测量装置确定所述导电构件的至少一部分的电阻。

    Thru-silicon-via structures
    3.
    发明授权
    Thru-silicon-via structures 有权

    公开(公告)号：US10388567B2

    公开(公告)日：2019-08-20

    申请号：US15724493

    申请日：2017-10-04

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Fen Chen ,  Mukta G. Farooq ,  Carole D. Graas ,  Xiao Hu Liu

    IPC: H01L21/768 ,  H01L23/48

    Abstract: Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material. The method further includes forming a stress absorption layer on the first conductive diffusion barrier. The method further includes forming a second conductive diffusion barrier on the stress absorption layer. The method further includes forming a copper plate on the second conductive diffusion barrier.

    Via leakage and breakdown testing
    5.
    发明授权
    Via leakage and breakdown testing 有权

    公开(公告)号：US09851398B2

    公开(公告)日：2017-12-26

    申请号：US14673185

    申请日：2015-03-30

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Fen Chen ,  Roger A. Dufresne ,  Charles W. Griffin ,  Kevin W. Kolvenbach

    IPC: G01R31/28 ,  H01L23/522

    CPC classification number: G01R31/2884 ,  G01R31/2831 ,  G01R31/2886 ,  H01L23/5226

    Abstract: Various particular embodiments include a via testing structure, including: a first terminal coupled to a first set of sensing lines in a top level of the structure; a second terminal coupled to a second set of sensing lines in the top level of the structure, wherein first set of sensing lines and the second set of sensing lines are disposed in a comb arrangement; a third terminal coupled to a third set of sensing lines in a bottom level of the structure; and a plurality of vias electrically coupling the second set of sensing lines in the top level of the structure to the third set of sensing lines in the bottom level of the structure, each via having a via top and a via bottom.

    DEVICE STRUCTURE WITH NEGATIVE RESISTANCE CHARACTERISTICS
    6.
    发明申请
    DEVICE STRUCTURE WITH NEGATIVE RESISTANCE CHARACTERISTICS 审中-公开
    具有负电阻特性的器件结构

    公开(公告)号：US20160225919A1

    公开(公告)日：2016-08-04

    申请号：US14612639

    申请日：2015-02-03

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Fen Chen ,  Carole D. Graas ,  Terence L. Kane ,  Michael A. Shinosky

    IPC: H01L29/94 ,  H01L29/32

    CPC classification number: H01L29/945 ,  H01L29/495 ,  H01L29/518 ,  H01L47/005

    Abstract: Device structures that exhibit negative resistance characteristics and fabrication methods for such device structures. A signal is applied to a metal layer of a metal-insulator-semiconductor capacitor to cause a breakdown of an insulator layer of the metal-insulator-semiconductor capacitor at a location. The breakdown at the location of the insulator layer causes the metal-insulator-semiconductor capacitor to exhibit negative resistance. The metal layer may be comprised of a polycrystalline metal. A grain of the polycrystalline metal may penetrate through the insulator layer and into a portion of a substrate at the location of the breakdown.

    Abstract translation: 显示负电阻特性的器件结构和这种器件结构的制造方法。 将信号施加到金属 - 绝缘体 - 半导体电容器的金属层，以使金属 - 绝缘体 - 半导体电容器的绝缘体层在一处发生击穿。 在绝缘体层的位置处的击穿导致金属 - 绝缘体 - 半导体电容器呈现负电阻。 金属层可以由多晶金属构成。 多晶金属的晶粒可以在击穿位置处穿过绝缘体层并进入衬底的一部分。

    Integrated circuit structure with through-semiconductor via
    9.
    发明授权
    Integrated circuit structure with through-semiconductor via 有权
    具有贯通半导体通孔的集成电路结构

    公开(公告)号：US09318414B2

    公开(公告)日：2016-04-19

    申请号：US14065454

    申请日：2013-10-29

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Fen Chen ,  Minhua Lu ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

    IPC: H01L23/48 ,  H01L23/522

    CPC classification number: H01L23/481 ,  H01L23/5226 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure generally provides for integrated circuit (IC) structures with through-semiconductor vias (TSV). In an embodiment, an IC structure may include a through-semiconductor via (TSV) embedded in a substrate, the TSV having a cap; a dielectric layer adjacent to the substrate; a metal layer adjacent to the dielectric layer; a plurality of vias each embedded within the dielectric layer and coupling the metal layer to the cap of the TSV at respective contact points, wherein the plurality of vias is configured to create a substantially uniform current density throughout the TSV.

    Abstract translation: 本公开通常提供具有贯穿半导体通孔（TSV）的集成电路（IC）结构。 在一个实施例中，IC结构可以包括嵌入在衬底中的贯穿半导体通孔（TSV），TSV具有帽; 与基板相邻的电介质层; 与介电层相邻的金属层; 多个通孔，每个通孔嵌入在电介质层内，并将金属层耦合到各个接触点处的TSV的盖，其中多个通孔被配置成在整个TSV中产生基本均匀的电流密度。

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