公开(公告)号：US10535606B2

公开(公告)日：2020-01-14

申请号：US16040752

申请日：2018-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Takashi Ando ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/768 ,  H01L29/51 ,  H01L29/66

Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

公开(公告)号：US10192867B1

公开(公告)日：2019-01-29

申请号：US15888401

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Puneet H. Suvarna ,  Hiroaki Niimi ,  Steven J. Bentley ,  Ali Razavieh

IPC: H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L29/45 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/285

Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.

公开(公告)号：US09842933B1

公开(公告)日：2017-12-12

申请号：US15180422

申请日：2016-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki Niimi ,  Kwan-Yong Lim ,  Steven John Bentley ,  Daniel Chanemougame

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/306 ,  H01L21/265 ,  H01L27/24 ,  H01L29/78

CPC classification number: H01L29/78618 ,  H01L21/265 ,  H01L21/30604 ,  H01L27/2454 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/7926 ,  H01L2029/7858

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

公开(公告)号：US20170125535A1

公开(公告)日：2017-05-04

申请号：US15272919

申请日：2016-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC: H01L29/45 ,  H01L29/161 ,  H01L29/417 ,  H01L27/092 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/285 ,  H01L29/08 ,  H01L21/768

CPC classification number: H01L29/45 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

公开(公告)号：US09543216B2

公开(公告)日：2017-01-10

申请号：US14731480

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki Niimi ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L21/823871 ,  H01L21/283 ,  H01L21/28525 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/76897 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/7839 ,  H01L2221/1063

Abstract: A trench contact epilayer in a semiconductor device is provided. Embodiments include forming trenches through an interlayer dielectric (ILD) over source/drain regions in NFET and PFET regions; depositing a conformal silicon nitride (SiN) layer over the ILD and in the trenches; removing the SiN layer in the PFET region; growing a germanium (Ge) epilayer over the source/drain regions in the PFET region; depositing metal over the ILD and in the trenches in the NFET and PFET regions; etching the metal in the NFET region to expose the conformal SiN layer; removing the SiN layer in the NFET region; growing a Group III-V epilayer over the source/drain regions in the NFET region; and depositing metal over the ILD and in the trenches in the NFET region.

Abstract translation: 提供半导体器件中的沟槽接触外延层。 实施例包括在NFET和PFET区域中的源/漏区上形成通过层间电介质（ILD）的沟槽; 在所述ILD和所述沟槽中沉积保形氮化硅（SiN）层; 去除PFET区域中的SiN层; 在PFET区域的源极/漏极区域上生长锗（Ge）外延层; 在ILD和NFET和PFET区域的沟槽中沉积金属; 蚀刻NFET区域中的金属以暴露共形SiN层; 去除NFET区域中的SiN层; 在NFET区域的源极/漏极区域上生长III-V族外延层; 以及在ILD上和在NFET区域的沟槽中沉积金属。

公开(公告)号：US20150380304A1

公开(公告)日：2015-12-31

申请号：US14314670

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Kwanyong Lim ,  Hiroaki Niimi

IPC: H01L21/768 ,  H01L23/532 ,  H01L29/66

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/41766 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of the bottom and walls of the contact trench. An x-metal layer can be deposited over the titanium liner on the bottom of the contact trench. A titanium nitride liner can then be formed on the walls of the contact trench. The x-metal layer prevents the nitriding of the titanium liner on the bottom of the contact trench during the formation of the nitride liner.

Abstract translation: 本发明的方面涉及在半导体器件中形成窄源极 - 漏极接触的方法。 可以将接触沟槽蚀刻到半导体器件的源极 - 漏极区域。 可以在该接触沟槽中沉积钛衬里，使得其覆盖接触沟槽的基本上整个底部和壁。 可以在接触沟槽的底部上的钛衬垫上沉积x-金属层。 然后可以在接触沟槽的壁上形成氮化钛衬垫。 在形成氮化物衬垫期间，x-金属层防止了接触沟槽底部的钛衬里的氮化。

公开(公告)号：US10854510B2

公开(公告)日：2020-12-01

申请号：US15687455

申请日：2017-08-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Kwanyong Lim ,  Hiroaki Niimi

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L29/417 ,  H01L23/485

Abstract: Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of the bottom and walls of the contact trench. An x-metal layer can be deposited over the titanium liner on the bottom of the contact trench. A titanium nitride liner can then be formed on the walls of the contact trench. The x-metal layer prevents the nitriding of the titanium liner on the bottom of the contact trench during the formation of the nitride liner.

公开(公告)号：US10381442B2

公开(公告)日：2019-08-13

申请号：US15954300

申请日：2018-04-16

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265 ,  H01L29/45 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

公开(公告)号：US10236292B1

公开(公告)日：2019-03-19

申请号：US16156082

申请日：2018-10-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Puneet H. Suvarna ,  Hiroaki Niimi ,  Steven J. Bentley ,  Ali Razavieh

IPC: H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/768 ,  H01L29/45 ,  H01L29/786

Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.

公开(公告)号：US10211094B2

公开(公告)日：2019-02-19

申请号：US15641861

申请日：2017-07-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/485 ,  H01L23/532 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.