公开(公告)号：US20160035743A1

公开(公告)日：2016-02-04

申请号：US14866878

申请日：2015-09-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Szu-Lin Cheng ,  Jack O. Chu ,  Isaac Lauer ,  Jeng-Bang Yau

IPC: H01L27/12 ,  H01L29/417 ,  H01L25/065 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L25/065 ,  H01L27/092 ,  H01L29/41783 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Source/drains are formed in source/drains regions. A stopping layer is formed on source/drains. Contact spacers are formed above gates. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other.

公开(公告)号：US09337281B2

公开(公告)日：2016-05-10

申请号：US14803910

申请日：2015-07-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cheng-Wei Cheng ,  Jack O. Chu ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/336 ,  H01L29/267 ,  H01L29/772 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L21/322 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/267 ,  H01L21/02387 ,  H01L21/02439 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/02664 ,  H01L21/28575 ,  H01L21/3228 ,  H01L29/452 ,  H01L29/66522 ,  H01L29/772 ,  H01L29/78

Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.

公开(公告)号：US09236250B2

公开(公告)日：2016-01-12

申请号：US13924064

申请日：2013-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jack O. Chu ,  Christos D. Dimitrakopoulos ,  Marcus O. Freitag ,  Alfred Grill ,  Timothy J. McArdle ,  Robert L. Wisnieff

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/267

CPC classification number: H01L21/02447 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/02527 ,  H01L21/02612 ,  H01L21/0262 ,  H01L21/02656 ,  H01L29/1606 ,  H01L29/267

Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.

公开(公告)号：US20160225853A1

公开(公告)日：2016-08-04

申请号：US15093053

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jack O. Chu ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  Chun-Yung Sung

IPC: H01L29/16 ,  H01L29/161 ,  H01L29/04

CPC classification number: H01L29/1606 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/184 ,  C01B2204/04 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/02667 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/161 ,  Y10T428/265

Abstract: A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.

Abstract translation: 半导体 - 碳合金层形成在半导体衬底的表面上，半导体衬底的表面可以是诸如硅衬底的市售半导体衬底。 半导体 - 碳合金层在高温退火期间被转化为至少一个石墨烯层，在此期间半导体 - 碳合金层表面上的半导体材料对碳原子有选择性的蒸发。 随着半导体原子被选择性地去除并且半导体 - 碳合金层的表面上的碳浓度增加，半导体 - 碳合金层顶层中剩余的碳原子聚结形成具有至少一个石墨烯单层的石墨烯层 。 因此，可以在直径为200mm或300mm的市售半导体衬底上提供石墨烯层。

公开(公告)号：US09548238B2

公开(公告)日：2017-01-17

申请号：US13964286

申请日：2013-08-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Szu-Lin Cheng ,  Jack O. Chu ,  Isaac Lauer ,  Jeng-Bang Yau

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76808 ,  H01L21/76895 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device, comprises forming an organic planarization layer on a plurality of gates on a substrate, wherein the plurality of gates each include a spacer layer thereon, forming an oxide layer on the organic planarization layer, removing a portion of the oxide layer to expose the organic planarization layer, stripping the organic planarization layer to form a cavity, patterning a direct lithographically-patternable gap dielectric on at least one of the gates in the cavity, and depositing a conductive contact in a remaining portion of the cavity.

Abstract translation: 一种半导体器件的制造方法，包括在基板上的多个栅极上形成有机平坦化层，其中，所述多个栅极各自包括间隔层，在所述有机平坦化层上形成氧化物层， 氧化层以暴露有机平坦化层，剥离有机平坦化层以形成空腔，在空腔中的至少一个栅极上图案化直接可光刻图案化的间隙电介质，以及在空腔的剩余部分中沉积导电接触 。

公开(公告)号：US09240326B2

公开(公告)日：2016-01-19

申请号：US14028022

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Szu-lin Cheng ,  Jack O. Chu ,  Isaac Lauer ,  Jeng-bang Yau

IPC: H01L29/76 ,  H01L29/40 ,  H01L23/48 ,  H01L21/283 ,  H01L21/768 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/283 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/785

Abstract: A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which an uppermost surface of each of the sacrificial contact structures is exposed. Each of the exposed sacrificial contact structures is then removed providing contact openings within the planarized middle-of-the-line dielectric material. A conductive metal-containing material is formed within each contact opening.

公开(公告)号：US09236477B2

公开(公告)日：2016-01-12

申请号：US14181832

申请日：2014-02-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jack O. Chu ,  Christos Dimitrakopoulos ,  Eric C. Harley ,  Judson R. Holt ,  Timothy J. McArdle ,  Matthew W. Stoker

IPC: H01L29/78 ,  H01L29/16 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/0243 ,  H01L21/02447 ,  H01L21/02527 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/66037 ,  H01L29/66795 ,  H01L29/7781

Abstract: Silicon-carbon alloy structures can be formed as inverted U-shaped structures around semiconductor fins by a selective epitaxy process. A planarization dielectric layer is formed to fill gaps among the silicon-carbon alloy structures. After planarization, remaining vertical portions of the silicon-carbon alloy structures constitute silicon-carbon alloy fins, which can have sublithographic widths. The semiconductor fins may be replaced with replacement dielectric material fins. In one embodiment, employing a patterned mask layer, sidewalls of the silicon-carbon alloy fins can be removed around end portions of each silicon-carbon alloy fin. An anneal is performed to covert surface portions of the silicon-carbon alloy fins into graphene layers. In one embodiment, each graphene layer can include only a horizontal portion in a channel region, and include a horizontal portion and sidewall portions in source and drain regions. If a patterned mask layer is not employed, each graphene layer can include only a horizontal portion.

Abstract translation: 硅碳合金结构可以通过选择性外延工艺形成为围绕半导体翅片的倒U形结构。 形成平坦化介电层以填充硅 - 碳合金结构之间的间隙。 在平坦化之后，硅 - 碳合金结构的剩余垂直部分构成可以具有亚光刻宽度的硅碳合金翅片。 半导体翅片可以用替换的介质材料翅片代替。 在一个实施例中，采用图案化掩模层，可以在每个硅 - 碳合金散热片的端部周围除去硅 - 碳合金散热片的侧壁。 执行退火以将硅碳合金翅片的表面部分隐藏成石墨烯层。 在一个实施例中，每个石墨烯层可以仅包括沟道区域中的水平部分，并且在源极和漏极区域中包括水平部分和侧壁部分。 如果不使用图案化掩模层，则每个石墨烯层可以仅包括水平部分。