公开(公告)号：US09793216B2

公开(公告)日：2017-10-17

申请号：US15006426

申请日：2016-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Jim Shih-Chun Liang ,  Domingo A. Ferrer Luppi ,  Atsushi Ogino ,  Andrew H. Simon ,  Michael P. Chudzik

IPC: H01L23/48 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266

Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.

公开(公告)号：US09431485B2

公开(公告)日：2016-08-30

申请号：US14580274

申请日：2014-12-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafaat Ahmed ,  Murshed M. Chowdhury ,  Aritra Dasgupta ,  Mohammad Hasanuzzaman ,  Shahrukh Akbar Khan ,  Joyeeta Nag

IPC: H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1045 ,  H01L21/265 ,  H01L21/26513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a finFET structure having an ion implanted intermediate region next to the channel region of a finFET gate. The intermediate region is formed in a manner to reduce or eliminate migration of the dopant to undoped regions of the finFET thus forming abrupt finFET junction.

Abstract translation: 一种在finFET栅极的沟道区域旁边形成离子注入中间区域的finFET结构的方法。 中间区域以减少或消除掺杂剂向finFET的未掺杂区域迁移的方式形成，从而形成突变的finFET结。

公开(公告)号：US20170236780A1

公开(公告)日：2017-08-17

申请号：US15485657

申请日：2017-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Shishir K. Ray ,  Andrew H. Simon ,  Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Michael P. Chudzik

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252

Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.

公开(公告)号：US20170213792A1

公开(公告)日：2017-07-27

申请号：US15006426

申请日：2016-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Jim Shih-Chun Liang ,  Domingo A. Ferrer Luppi ,  Atsushi Ogino ,  Andrew H. Simon ,  Michael P. Chudzik

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266

Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.

公开(公告)号：US09362230B1

公开(公告)日：2016-06-07

申请号：US14722302

申请日：2015-05-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lawrence A. Clevenger ,  Vincent J. McGahay ,  Joyeeta Nag ,  Yiheng Xu

IPC: H01L21/265 ,  H01L23/532 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76892 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/3105 ,  H01L21/76825 ,  H01L21/76885 ,  H01L23/5256 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrically conductive structures and methods of making electrically conductive structures. The methods include providing a dielectric layer of a material having a top surface and a dielectric constant of less than 3; rastering a gas cluster ion beam to form a patterned modified surface region of the top surface of the dielectric layer; and selectively forming an electrically conductive thin film on the patterned modified surface region using atomic layer deposition.

Abstract translation: 导电结构和制造导电结构的方法。 所述方法包括提供具有上表面和介电常数小于3的材料的电介质层; 清理气体簇离子束以形成电介质层的顶表面的图案化的改性表面区域; 并使用原子层沉积在图案化的改性表面区域上选择性地形成导电薄膜。

公开(公告)号：US20160086849A1

公开(公告)日：2016-03-24

申请号：US14490792

申请日：2014-09-19

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Joyeeta Nag ,  Andrew H. Simon ,  Shishir Ray

IPC: H01L21/768

CPC classification number: H01L21/76894 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/00

Abstract: In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.

Abstract translation: 密封铜线的原位熔融和结晶可以通过激光退火进行纳秒的持续时间。 选择激光照射的强度，使得熔融铜浸润互连界面，从而形成增加电子的镜面散射的界面结合装置。 纳秒级温度淬火保持形成的界面结合。 同时，密封铜互连的快速结晶过程平均导致大的铜晶粒，通常大于80nm的横向尺寸。 退火过程的典型持续时间为约10秒至约100秒的纳秒。 尽管由于超短时间的高退火温度，层间低k介电材料没有劣化，从而防止原子在电介质材料内的集体运动。

公开(公告)号：US09748235B2

公开(公告)日：2017-08-29

申请号：US15013169

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Aritra Dasgupta ,  Benjamin G. Moser ,  Mohammad Hasanuzzaman ,  Murshed M. Chowdhury ,  Shahrukh A. Khan ,  Shafaat Ahmed ,  Joyeeta Nag

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/518

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.

公开(公告)号：US20170221889A1

公开(公告)日：2017-08-03

申请号：US15013169

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Aritra Dasgupta ,  Benjamin G. Moser ,  Mohammad Hasanuzzaman ,  Murshed M. Chowdhury ,  Shahrukh A. Khan ,  Shafaat Ahmed ,  Joyeeta Nag

IPC: H01L27/088 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/518

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.

公开(公告)号：US09679810B1

公开(公告)日：2017-06-13

申请号：US15041203

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Shishir K. Ray ,  Andrew H. Simon ,  Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Michael P. Chudzik

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53252

Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.

公开(公告)号：US09412658B2

公开(公告)日：2016-08-09

申请号：US14490792

申请日：2014-09-19

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Joyeeta Nag ,  Andrew H. Simon ,  Shishir Ray

IPC: H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76894 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/00

Abstract: In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.

Abstract translation: 密封铜线的原位熔融和结晶可以通过激光退火进行纳秒的持续时间。 选择激光照射的强度，使得熔融铜浸润互连界面，从而形成增加电子的镜面散射的界面结合装置。 纳秒级温度淬火保持形成的界面结合。 同时，密封铜互连的快速结晶过程平均导致大的铜晶粒，通常大于80nm的横向尺寸。 退火过程的典型持续时间为约10秒至约100秒的纳秒。 尽管由于超短时间的高退火温度，层间低k介电材料没有劣化，从而防止原子在电介质材料内的集体运动。