公开(公告)号：US09711511B1

公开(公告)日：2017-07-18

申请号：US15193867

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Ryan Ryoung-Han Kim ,  Motoi Ichihashi ,  Youngtag Woo ,  Deepak Nayak

IPC: H01L29/66 ,  H01L27/11 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L27/1104 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/513 ,  H01L29/7827

Abstract: A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors.

公开(公告)号：US20160163604A1

公开(公告)日：2016-06-09

申请号：US14674924

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim ,  Kwan-Yong Lim ,  Chanro Park

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823878 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin.

Abstract translation: 本文公开的一种说明性方法包括在两个有源栅极和伪栅极的鳍片的上方形成第一牺牲栅极结构，去除用于伪栅极的第一牺牲栅极结构，以便限定在离开第一牺牲栅极结构的同时露出鳍片的空腔 对于完整的两个有源栅极，蚀刻通过空腔以在腔下方的鳍形成沟槽，形成用于伪栅极的第二牺牲栅极结构，去除用于两个有源栅极和第二牺牲栅极结构的第一牺牲栅极结构 为了形成用于两个有源栅极和虚拟栅极的替代栅极腔，并且在每个替代栅极腔中形成替代栅极结构，其中用于伪栅极的替代栅极结构延伸到沟槽中 翅膀

公开(公告)号：US09362181B1

公开(公告)日：2016-06-07

申请号：US14674924

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim ,  Kwan-Yong Lim ,  Chanro Park

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/823878 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin.

Abstract translation: 本文公开的一种说明性方法包括在两个有源栅极和伪栅极的鳍片的上方形成第一牺牲栅极结构，去除用于伪栅极的第一牺牲栅极结构，以便限定在离开第一牺牲栅极结构的同时露出鳍片的空腔 对于完整的两个有源栅极，蚀刻通过空腔以在腔下方的鳍形成沟槽，形成用于伪栅极的第二牺牲栅极结构，去除用于两个有源栅极和第二牺牲栅极结构的第一牺牲栅极结构 为了形成用于两个有源栅极和虚拟栅极的替代栅极腔，并且在每个替代栅极腔中形成替代栅极结构，其中用于伪栅极的替代栅极结构延伸到沟槽中 翅膀

公开(公告)号：US09209037B2

公开(公告)日：2015-12-08

申请号：US14196931

申请日：2014-03-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Jin Cho ,  Ryan Ryoung-Han Kim

IPC: H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/845

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming fin structures in a selected area of a semiconductor substrate. The method includes covering the fin structures and the semiconductor substrate with a mask and forming a trench in the mask to define no more than two exposed fin structures in the selected area. Further, the method includes removing the exposed fin structures to provide the selected area with a desired number of fin structures.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底的选定区域中形成鳍结构。 该方法包括用掩模覆盖翅片结构和半导体衬底，并在掩模中形成沟槽，以在所选择的区域中限定不超过两个暴露的翅片结构。 此外，该方法包括去除暴露的翅片结构以向选定区域提供所需数量的翅片结构。

公开(公告)号：US09543416B2

公开(公告)日：2017-01-10

申请号：US14536026

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ryan Ryoung-Han Kim

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L21/308 ,  H01L27/11

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L27/1104 ,  H01L29/0642 ,  H01L29/66553 ,  H01L29/6681

Abstract: One illustrative method disclosed herein includes, among other things, forming a first plurality of fins in the first region of the substrate, a second plurality of fins in the second region of the substrate, and a space in the substrate between two adjacent fins in the second region that corresponds to a first isolation region to be formed in the second region, forming a fin removal masking layer above the first and second regions of the substrate, wherein the fin removal masking layer has an opening positioned above at least a portion of at least one of the first plurality of fins, while masking all of the second plurality of fins in the second region and the space for the first isolation region, and performing an etching process through the first opening to remove the portions of the at least one of the first plurality of fins.

Abstract translation: 本文公开的一种说明性方法包括在衬底的第一区域中形成第一多个鳍片，在衬底的第二区域中形成第二多个鳍片，以及在衬底中的两个相邻鳍片之间的空间 第二区域，其对应于将形成在第二区域中的第一隔离区域，在基板的第一和第二区域上方形成散热片去除掩模层，其中散热片移除掩模层具有位于至少一部分上方的开口 在第二区域中的所有第二多个散热片和第一隔离区域的空间中遮挡所有的第一多个散热片中的至少一个，并且通过第一开口执行蚀刻处理以去除至少一个 第一组多个翅片。

公开(公告)号：US09362403B2

公开(公告)日：2016-06-07

申请号：US14817628

申请日：2015-08-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Ryan Ryoung-Han Kim ,  William J. Taylor, Jr.

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess that have an outer perimeter surface that contacts at least a portion of an interior perimeter surface of the recess and forming at least one source/drain contact structure for each of the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure. The upper surface of each of the buried fin contact structures is positioned below an upper surface of the raised isolation structure and an outer perimeter surface of each of the buried fin contact structures contacts at least a portion of an interior perimeter surface of the recess.

公开(公告)号：US09299781B2

公开(公告)日：2016-03-29

申请号：US14242416

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  William J. Taylor, Jr. ,  Ryan Ryoung-Han Kim

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851

Abstract: One illustrative device disclosed herein includes, among other things, an active region defined in a semiconductor substrate, a layer of material positioned above the substrate, a plurality of laterally spaced-apart source/drain trenches formed in the layer of material above the active region, a conductive source/drain contact structure formed within each of the source/drain trenches, a gate trench formed at least partially in the layer of material between the spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure.

Abstract translation: 本文公开的一个说明性器件尤其包括限定在半导体衬底中的有源区，位于衬底上方的材料层，形成在有源区上方的材料层中的多个横向间隔开的源极/漏极沟槽 形成在每个源极/漏极沟槽内的导电源极/漏极接触结构，至少部分地形成在材料层中的间隔开的源极/漏极沟槽之间的材料层中的栅极沟槽，其中层的部分 的材料保持位于源极/漏极沟槽和栅极沟槽之间，位于栅极沟槽内的栅极结构以及位于栅极结构之上的栅极盖层。

公开(公告)号：US20150318181A1

公开(公告)日：2015-11-05

申请号：US14267959

申请日：2014-05-02

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Ryan Ryoung-Han Kim

IPC: H01L21/308 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L21/823431

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a patternable structure having first and second regions and including upper and lower mandrel layers. The method etches upper mandrels from the upper mandrel layer in the first and second regions. The method includes forming first upper spacer structures having a first width adjacent upper mandrels in the first region and forming second upper spacer structures having a second width not equal to the first width adjacent upper mandrels in the second region. The method etches the lower mandrel layer using the first and second upper spacer structures as an etch mask to form lower mandrels. Further, the method includes forming spacers adjacent the lower mandrels and etching a material using the spacers as an etch mask to form variably spaced features.

Abstract translation: 提供了制造集成电路和形成用于制造集成电路的掩模的方法。 一种用于制造集成电路的示例性方法包括提供具有第一和第二区域并且包括上部和下部心轴层的可图案化结构。 该方法在第一和第二区域中从上心轴层蚀刻上心轴。 该方法包括形成在第一区域中具有与上心轴相邻的第一宽度的第一上间隔结构，并且形成第二上间隔结构，其具有不等于第二区中相邻上心轴的第一宽度的第二宽度。 该方法使用第一和第二上间隔结构蚀刻下心轴层作为蚀刻掩模以形成下心轴。 此外，该方法包括形成邻近下心轴的间隔物，并使用间隔物蚀刻材料作为蚀刻掩模以形成可变间隔的特征。

公开(公告)号：US20150279935A1

公开(公告)日：2015-10-01

申请号：US14242416

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  William J. Taylor, JR. ,  Ryan Ryoung-Han Kim

IPC: H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/0847 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851

Abstract: One illustrative device disclosed herein includes, among other things, an active region defined in a semiconductor substrate, a layer of material positioned above the substrate, a plurality of laterally spaced-apart source/drain trenches formed in the layer of material above the active region, a conductive source/drain contact structure formed within each of the source/drain trenches, a gate trench formed at least partially in the layer of material between the spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure.

Abstract translation: 本文公开的一个说明性器件尤其包括限定在半导体衬底中的有源区，位于衬底上方的材料层，形成在有源区上方的材料层中的多个横向间隔开的源极/漏极沟槽 形成在每个源极/漏极沟槽内的导电源极/漏极接触结构，至少部分地形成在材料层中的间隔开的源极/漏极沟槽之间的材料层中的栅极沟槽，其中层的部分 的材料保持位于源极/漏极沟槽和栅极沟槽之间，位于栅极沟槽内的栅极结构以及位于栅极结构之上的栅极盖层。

公开(公告)号：US10580779B2

公开(公告)日：2020-03-03

申请号：US15903203

申请日：2018-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Ryan Ryoung-Han Kim

IPC: H01L27/11 ,  G11C8/14 ,  H01L23/522 ,  H01L21/768 ,  H01L27/105 ,  H01L21/48 ,  H01L23/50

Abstract: A memory cell includes vertical transistors including first and second pass gate (PG) transistors, first and second pull-up (PU1 and PU2) transistors, and first and second pull-down (PD1 and PD2) transistors. A first bottom electrode connects bottom source/drain (SD) regions of PU1 and PU2. A second bottom electrode connects bottom SD regions of PD1 and PD2. A first shared contact connects the top SD region of PU2 to the gate structure of PU1. A second shared contact connects the top SD region of PD1 to the gate structure of PD2. A first top electrode is connected to the top SD regions of PG1, PU1 and the second shared contact to define a first storage node of the memory cell. A second top electrode is connected to the top SD regions of PG2, PU2 and the first shared contact to define a second storage node of the memory cell.