公开(公告)号：US09209186B1

公开(公告)日：2015-12-08

申请号：US14315885

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro Togo ,  Changyong Xiao ,  Yiqun Liu ,  Dina H. Triyoso ,  Rohit Pal

IPC: H01L21/00 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/324 ,  H01L21/265 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract translation: 三个p型器件和在同一衬底上共同制造的三个n型器件提供了一个最低，低和规则阈值电压范围。 对于p型器件，使用栅极结构中的p型功函数金属的附加厚层并对其进行氧化来实现最低的范围，低Vt由厚的p型功函数金属单独实现 ，并且通过p型功函数金属的较薄层实现常规Vt。 对于n型器件，最低的Vt是通过用砷，氩，硅或锗注入氮化钽而不是在栅极结构中添加任何附加的p型功函数金属来实现的，低Vt是通过不添加 额外的p型功函数金属，而常规Vt是用最薄层的p型功函金属实现的。

公开(公告)号：US09087720B1

公开(公告)日：2015-07-21

申请号：US14450535

申请日：2014-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Manfred Eller ,  Wanxun He ,  Jie Chen

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L21/26513 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming FinFETs with reduced series resistance includes providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate, a gate disposed over a first portion of the fin, and a first sidewall spacer disposed over the fin and adjacent to the gate, increasing epitaxially the thickness of a second portion of the fin disposed outside the gate and the first sidewall spacer, and forming a second sidewall spacer disposed over the second portion of the fin and adjacent to the first sidewall spacer. A thickness of the second portion of the fin disposed under the second spacer is equal to or greater than a thickness of the first portion of the fin disposed under the gate.

Abstract translation: 用于形成具有降低的串联电阻的FinFET的方法包括提供包括半导体衬底的中间半导体结构，设置在半导体衬底上的鳍，设置在鳍的第一部分上的栅极和设置在鳍上并邻近 到外部延伸设置在栅极和第一侧壁间隔物外部的翅片的第二部分的厚度，以及形成设置在翅片的第二部分上并邻近第一侧壁间隔物的第二侧壁间隔物。 设置在第二间隔件下方的翅片的第二部分的厚度等于或大于设置在浇口下方的翅片的第一部分的厚度。

公开(公告)号：US09793358B2

公开(公告)日：2017-10-17

申请号：US14267541

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Xiang Hu ,  Changyong Xiao ,  Wanxun He

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/161 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/7853

Abstract: A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures.

公开(公告)号：US20160049468A1

公开(公告)日：2016-02-18

申请号：US14823319

申请日：2015-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Wanxun He ,  Hongliang Shen

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0646 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure.

Abstract translation: 公开了一种集成电路产品，其包括限定第一，第二和第三鳍片的半导体衬底中的多个沟槽，其中散热片并排，并且其中第二鳍片位于第一和第三鳍片之间， 多个沟槽中的绝缘材料层，使得第一，第二和第三鳍片的期望高度位于绝缘材料层的上表面上方，限定在第二鳍片中的凹部，其至少部分地限定在第 所述绝缘材料层，在所述第二鳍片的凹陷部分上的空腔中的SDB隔离结构，其中所述SDB隔离结构具有位于所述绝缘材料层的上表面上方的上表面，以及用于 晶体管位于SDB隔离结构之上。

公开(公告)号：US20150333121A1

公开(公告)日：2015-11-19

申请号：US14810167

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US09171752B1

公开(公告)日：2015-10-27

申请号：US14457325

申请日：2014-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Wanxun He ,  Hongliang Shen

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0646 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: One illustrative method disclosed herein includes, among other things, forming first, second and third fins that are arranged side-by-side, forming a recessed layer of insulating material in a plurality of trenches, after recessing the layer of insulating material, masking the first and second fins while exposing a portion of the axial length of the second fin, removing the exposed portion of the second fin so as to thereby define a cavity in the recessed layer of insulating material, forming an SDB isolation structure in the cavity, wherein the SDB isolation structure has an upper surface that is positioned above the recessed upper surface of the recessed layer of insulating material, removing the masking layer, and forming a gate structure for a transistor above the SDB isolation structure.

Abstract translation: 本文公开的一种说明性方法包括形成并排布置的第一，第二和第三鳍片，在凹陷绝缘材料层之后，在多个沟槽中形成绝缘材料的凹陷层，掩蔽 第一和第二鳍片，同时暴露第二鳍片的轴向长度的一部分，去除第二鳍片的暴露部分，从而在绝缘材料的凹陷层中限定空腔，在空腔中形成SDB隔离结构，其中 SDB隔离结构具有位于绝缘材料的凹陷层的凹陷的上表面上方的上表面，去除掩模层，并且在SDB隔离结构之上形成用于晶体管的栅极结构。

公开(公告)号：US09508794B2

公开(公告)日：2016-11-29

申请号：US15002000

申请日：2016-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Xiang Hu ,  Wanxun He

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20

CPC classification number: H01L29/0657 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/201

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract translation: 非平面半导体结构包括混合的n型和p型凸起半导体结构，例如具有在其顶表面上生长的外延结构的散热片，例如外延硅和硅锗，天然生长成菱形。 外延结构的表面积通过去除其部分而增加，当另一种类型生长然后随后通过去除而修饰时，掩蔽每种类型。 移除可以与类似于Y形的相应凸起结构的颈部一起产生多头（例如，双头）外延结构。

公开(公告)号：US09385192B2

公开(公告)日：2016-07-05

申请号：US14810167

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

公开(公告)号：US09299608B2

公开(公告)日：2016-03-29

申请号：US14281454

申请日：2014-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Min-hwa Chi

IPC: H01L21/28 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/485 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor, planar or non-planar (e.g., FinFET), includes T-shaped contacts to the source, drain and gate. The top portion of the T-shaped contact is wider than the bottom portion, the bottom portion complying with design rule limits. A conductor-material filled trench through a multi-layer etching stack above the transistor provides the top portions of the T-shaped contacts. Tapered spacers along inner sidewalls of the top contact portion prior to filling allow for etching a narrower bottom trench down to the gate, and to the source/drain for silicidation prior to filling.

Abstract translation: 晶体管，平面或非平面（例如，FinFET）包括到源极，漏极和栅极的T形接触。 T形接触件的顶部比底部宽，底部符合设计规则限制。 通过晶体管上方的多层蚀刻堆叠的导体材料填充沟槽提供了T形触头的顶部。 在填充之前，顶部接触部分的内侧壁上的锥形间隔物允许在填充之前将较窄的底部沟槽蚀刻到栅极和源极/漏极以进行硅化。

公开(公告)号：US09123771B2

公开(公告)日：2015-09-01

申请号：US13765723

申请日：2013-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。