公开(公告)号：US20160276345A1

公开(公告)日：2016-09-22

申请号：US15049391

申请日：2016-02-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong YU ,  Bingwu LIU ,  Hui ZANG ,  Lun ZHAO

IPC: H01L27/088 ,  H01L29/161 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/3083 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Method for forming FinFET source/drain regions with reduced field oxide loss and the resulting devices are disclosed. Embodiments include forming silicon fins separated by a field oxide on a silicon substrate; recessing the field oxide to reveal an upper portion of the silicon fins; forming a spacer layer conformally over the upper portion of the fins and over the field oxide; filling spaces between the fins with a material having high selectivity with the spacer layer; recessing the material; removing the spacer layer above an upper surface of the material; removing the material; recessing the upper portion of the fins; and epitaxially growing source/drain regions on the recessed fins.

Abstract translation: 公开了用于形成具有减小的场氧化物损耗的FinFET源极/漏极区域的方法以及所得到的器件。 实施例包括在硅衬底上形成由场氧化物分离的硅散热片; 凹陷场氧化物以露出硅散热片的上部; 在翅片的上部和场氧化物上方形成间隔层; 用具有间隔层的高选择性的材料填充翅片之间的空间; 凹陷材料; 在所述材料的上表面上方移除所述间隔层; 去除材料; 使翅片的上部凹陷; 并且在凹陷散热片上外延生长源极/漏极区域。

公开(公告)号：US20160163702A1

公开(公告)日：2016-06-09

申请号：US14560049

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Yue HU ,  Xin WANG ,  Yong Meng LEE ,  Wen-Pin PENG ,  Lun ZHAO ,  Wei-Hua TONG

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions

Abstract translation: 公开了用于形成沟槽硅化物而不使硅源极/漏极区和所得到的器件气蚀的方法。 实施例包括在基板上形成第一和第二伪栅极，每个具有相对侧的间隔物; 在第一伪栅极的相对侧形成eSiGe源极/漏极区; 在所述第二虚拟栅极的相对侧形成凸起的源极/漏极区域; 在每个eSiGe和升高的源极/漏极区域上形成硅帽; 在第一和第二虚拟门之间和之间形成ILD; 分别用第一和第二HKMG代替第一和第二虚拟门; 在每个eSiGe和升高的源极/漏极区域上形成穿过ILD的接触沟槽进入硅帽; 并在eSiGe上形成硅化物并升高源极/漏极区域

公开(公告)号：US20150017774A1

公开(公告)日：2015-01-15

申请号：US13938786

申请日：2013-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Hua TONG ,  Hong YU ,  Jin Ping LIU ,  Hyucksoo YANG ,  Lun ZHAO ,  Chandra REDDY

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/02236 ,  H01L21/823431 ,  H01L29/7854

Abstract: Thermal oxidation treatment methods and processes used during fabrication of semiconductor devices are provided. One method includes, for instance: obtaining a device with at least one cavity etched into the device; performing a thermal oxidation treatment to the at least one cavity; and cleaning the at least one cavity. One process includes, for instance: providing a semiconductor device with a substrate, at least one layer over the substrate and at least one fin; forming at least one gate over the fin; doping at least one region below the fin; applying a spacer layer over the device; etching the spacer layer to expose at least a portion of the gate material; etching a cavity into the at least one fin; etching a shaped opening into the cavity; performing thermal oxidation processing on the at least one cavity; and growing at least one epitaxial layer on an interior surface of the cavity.

Abstract translation: 提供了在制造半导体器件期间使用的热氧化处理方法和工艺。 一种方法包括例如：获得具有蚀刻到该装置中的至少一个腔的装置; 对所述至少一个腔进行热氧化处理; 以及清洁所述至少一个腔。 一个过程包括例如：提供具有衬底的半导体器件，衬底上的至少一个层和至少一个鳍; 在翅片上形成至少一个闸门; 掺杂鳍片以下的至少一个区域; 在该装置上施加间隔层; 蚀刻间隔层以露出栅极材料的至少一部分; 将空腔蚀刻到所述至少一个翅片中; 将成形的开口蚀刻到空腔中; 在所述至少一个腔体上进行热氧化处理; 以及在腔的内表面上生长至少一个外延层。

公开(公告)号：US20150140756A1

公开(公告)日：2015-05-21

申请号：US14084756

申请日：2013-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong YU ,  Seong Yeol MUN ,  Bingwu LIU ,  Lun ZHAO ,  Richard J. CARTER ,  Manfred ELLER

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Circuit fabrication methods are provided which include, for example: providing one or more gate structures disposed over a substrate structure, the substrate structure including a first region and a second region; forming a plurality of U-shaped cavities extending into the substrate structure in the first region and the second region thereof, where at least one first cavity of the plurality of U-shaped cavities is disposed adjacent in one gate structure in the first region; and expanding the at least one first cavity further into the substrate structure to at least partially undercut the one gate structure, without expanding at least one second cavity of the plurality of U-shaped cavities, where forming the plurality of U-shaped cavities facilitates fabricating the circuit structure. In one embodiment, the circuit structure includes first and second transistors, having different device architectures, the first transistor having a higher mobility characteristic than the second transistor.

Abstract translation: 提供了电路制造方法，其包括例如：提供设置在衬底结构上方的一个或多个栅极结构，所述衬底结构包括第一区域和第二区域; 在所述第一区域和所述第二区域中形成延伸到所述衬底结构中的多个U形空腔，其中所述多个U形空腔中的至少一个第一空腔邻近所述第一区域中的一个栅极结构设置; 以及将所述至少一个第一空腔进一步扩展到所述衬底结构中以至少部分地切割所述一个栅极结构，而不扩展所述多个U形空腔中的至少一个第二空腔，其中形成所述多个U形空腔有助于制造 电路结构。 在一个实施例中，电路结构包括具有不同器件结构的第一和第二晶体管，第一晶体管具有比第二晶体管更高的迁移率特性。

公开(公告)号：US20150140751A1

公开(公告)日：2015-05-21

申请号：US14085906

申请日：2013-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong YU ,  Huang LIU ,  Lun ZHAO ,  Richard J. CARTER

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: Circuit fabrication methods are provided which include, for example: providing the circuit structure with at least one gate structure extending over a first region and a second region of a substrate structure, the at least one gate structure including a capping layer; and modifying an etch property of at least a portion of the capping layer of the at least one gate structure, where the modified etch property inhibits etching of the at least one gate structure during a first etch process facilitating fabrication of at least one first transistor in the first region and inhibits etching of the at least one gate structure during a second etch process facilitating fabrication of at least one second transistor in the second region.

Abstract translation: 提供了电路制造方法，其包括例如：为电路结构提供在衬底结构的第一区域和第二区域上延伸的至少一个栅极结构，所述至少一个栅极结构包括封盖层; 以及修改所述至少一个栅极结构的覆盖层的至少一部分的蚀刻特性，其中所述修改的蚀刻性能在第一蚀刻工艺期间禁止蚀刻所述至少一个栅极结构，促进制造至少一个第一晶体管 所述第一区域并且在第二蚀刻工艺期间抑制所述至少一个栅极结构的蚀刻，促进在所述第二区域中制造至少一个第二晶体管。

公开(公告)号：US20150333067A1

公开(公告)日：2015-11-19

申请号：US14812500

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Andy WEI ,  Lun ZHAO ,  Dae Geun YANG ,  Jin Ping LIU ,  Tien-Ying LUO ,  Guillaume BOUCHE ,  Mariappan HARIHARAPUTHIRAN ,  Churamani GAIRE

IPC: H01L27/092 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

公开(公告)号：US20150129983A1

公开(公告)日：2015-05-14

申请号：US14079757

申请日：2013-11-14

Applicant: Globalfoundries Inc.

Inventor： Hong YU ,  Hyucksoo YANG ,  Bingwu LIU ,  Puneet KHANNA ,  Lun ZHAO

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having extended embedded stress elements. The methods include, for example: providing a gate structure extending over a fin extending above a substrate; using isotropic etching and anisotropic etching to form an extended cavity within the fin, where the extended cavity in part undercuts the gate structure, and where the using of the isotropic etching and the anisotropic etching deepens the extended cavity into the fin below the undercut gate structure; and forming an embedded stress element at least partially within the extended cavity, including below the gate structure.

Abstract translation: 鳍型晶体管制造方法和结构被提供具有延伸的嵌入应力元件。 所述方法包括例如：提供在衬底上延伸的翅片上延伸的栅极结构; 使用各向同性蚀刻和各向异性蚀刻在翅片内形成延伸空腔，其中延伸空腔部分地削弱了栅极结构，并且其中使用各向同性蚀刻和各向异性蚀刻将扩展腔加深到底切栅结构下方的翅片 ; 以及至少部分地在所述延伸空腔内形成嵌入的应力元件，包括在所述栅极结构下方。

公开(公告)号：US20150091094A1

公开(公告)日：2015-04-02

申请号：US14043243

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Andy WEI ,  Lun ZHAO ,  Dae Geun YANG ,  Jin Ping LIU ,  Tien-Ying LUO ,  Guillaume BOUCHE ,  Mariappan HARIHARAPUTHIRAN ,  Churamani GAIRE

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

Abstract translation: 提供了用FinFET形成半导体器件的器件和方法。 一种方法包括例如：获得具有衬底和至少一个浅沟槽隔离区域的中间半导体器件; 在中间半导体器件上沉积硬掩模层; 蚀刻硬掩模层以形成至少一个翅片硬掩模; 以及在所述至少一个翅片硬掩模和所述基底的至少一部分上沉积至少一个牺牲栅极结构。 一个中间半导体器件包括例如：具有至少一个浅沟槽隔离区域的衬底; 在衬底上的至少一个翅片硬掩模; 至少一个翅片硬掩模上的至少一个牺牲栅极结构; 设置在所述至少一个牺牲栅极结构上的至少一个间隔物; 以及至少一个pFET区域和至少一个生长到衬底中的nFET区域。