公开(公告)号：US09698241B1

公开(公告)日：2017-07-04

申请号：US15071600

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Suraj K. Patil ,  Min-Hwa Chi ,  Mitsuhiro Togo

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one embodiment, a method for fabricating integrated circuits includes forming a gate dielectric overlying a substrate, and forming a base work function layer that includes tungsten overlying the gate dielectric. The base work function layer overlies the gate dielectric in a first and second region, where the first region is one of a pFET region or an nFET region and the second region is the other of the pFET region or the nFET region. A mask is formed over the first region, and then the second region is exposed. A work function value of the base work function layer in the second region is altered to produce a modified work function layer. The mask is removed from the over the first region, and a gate electrode is formed overlying the base and modified work function layers.

公开(公告)号：US09508602B2

公开(公告)日：2016-11-29

申请号：US14593183

申请日：2015-01-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro Togo

IPC: H01L21/324 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/66 ,  H01L29/32 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L29/167

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26593 ,  H01L21/324 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/32 ,  H01L29/66795

Abstract: Semiconductor structures and methods of fabrication are provided for, for instance, inhibiting diffusion of active dopant within a semiconductor material. A diffusion-suppressing dopant is implanted via, an implanting process under controlled temperature, into a semiconductor material of a semiconductor structure to define a diffusion-suppressed region within the semiconductor material. One or more active regions are established within the diffusion-suppressed region of the semiconductor structure by, for example, implanting an active dopant into the semiconductor material. The implanting of the diffusion-suppressing dopant facilitates inhibiting diffusion of the active dopant within the diffusion-suppressed region.

Abstract translation: 提供半导体结构和制造方法用于例如抑制半导体材料内的活性掺杂剂的扩散。 通过在受控温度下的注入工艺将半导体结构的半导体材料注入扩散抑制掺杂剂，以限定半导体材料内的扩散抑制区域。 通过例如将半导体材料中的活性掺杂剂注入，在半导体结构的扩散抑制区域内建立一个或多个有源区。 扩散抑制掺杂剂的注入有助于抑制活性掺杂剂在扩散抑制区域内的扩散。

公开(公告)号：US09419103B2

公开(公告)日：2016-08-16

申请号：US14593264

申请日：2015-01-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro Togo

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L21/3215 ,  H01L21/324

CPC classification number: H01L29/66568 ,  H01L21/26513 ,  H01L21/32155 ,  H01L21/324 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

Abstract: Field-effect transistor and method of fabrication are provided for, for instance, providing a gate structure disposed over a substrate. The fabricating method further includes forming a source and drain region within the substrate separated by a channel region, the channel region underlying, at least partially, the gate structure. Forming further includes implanting at least one dopant at a pre-selected temperature into the source and drain region to facilitate increasing a concentration of the at least one dopant within the source and drain region, where the implanting of the at least one dopant at the pre-selected temperature facilitates reducing contact resistance of the source and drain region and increasing charge carrier mobility through the channel region.

Abstract translation: 提供场效应晶体管和制造方法，例如提供设置在衬底上的栅极结构。 制造方法还包括在衬底内形成源极和漏极区域，由沟道区域分隔开，沟道区域至少部分地位于栅极结构的下方。 形成还包括将预选温度的至少一种掺杂剂注入到源极和漏极区域中以有助于增加源极和漏极区域内的至少一种掺杂剂的浓度，其中在预处理期间注入至少一种掺杂剂 - 选择的温度有助于降低源区和漏区的接触电阻，并增加通过沟道区的电荷载流子迁移率。

公开(公告)号：US20160351675A1

公开(公告)日：2016-12-01

申请号：US14721822

申请日：2015-05-26

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Suraj K. Patil ,  Mitsuhiro Togo

IPC: H01L29/423 ,  H01L29/49 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/225

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes defining a pFET region and an nFET region of a semiconductor substrate. The method deposits a first work function material including tungsten and nitride over the pFET region and the nFET region of the semiconductor substrate. The method includes selectively modifying the first work function material in a selected region. Further, the method includes depositing a metal fill over the first work function material in the pFET region and the nFET region of the semiconductor substrate.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括限定半导体衬底的pFET区和nFET区。 该方法在pFET区域和半导体衬底的nFET区域上沉积包括钨和氮化物的第一功函材料。 该方法包括选择性地修改选定区域中的第一功函数材料。 此外，该方法包括在pFET区域和半导体衬底的nFET区域中的第一功函数材料上沉积金属填充物。

公开(公告)号：US09209186B1

公开(公告)日：2015-12-08

申请号：US14315885

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro Togo ,  Changyong Xiao ,  Yiqun Liu ,  Dina H. Triyoso ,  Rohit Pal

IPC: H01L21/00 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/324 ,  H01L21/265 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract translation: 三个p型器件和在同一衬底上共同制造的三个n型器件提供了一个最低，低和规则阈值电压范围。 对于p型器件，使用栅极结构中的p型功函数金属的附加厚层并对其进行氧化来实现最低的范围，低Vt由厚的p型功函数金属单独实现 ，并且通过p型功函数金属的较薄层实现常规Vt。 对于n型器件，最低的Vt是通过用砷，氩，硅或锗注入氮化钽而不是在栅极结构中添加任何附加的p型功函数金属来实现的，低Vt是通过不添加 额外的p型功函数金属，而常规Vt是用最薄层的p型功函金属实现的。

公开(公告)号：US20180358272A1

公开(公告)日：2018-12-13

申请号：US15622061

申请日：2017-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mitsuhiro Togo ,  Ram Asra ,  Xing Zhang ,  Palanivel Balasubramaniam

IPC: H01L21/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L22/20 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/42376

Abstract: At least one method, apparatus and system are disclosed for controlling threshold voltage values for a plurality of transistor devices. Determine a first threshold voltage of a first transistor gate comprising a first gate channel having a first length. Determine a second length of a second gate channel of a second transistor gate. Determining a process adjustment of the second gate based on the second length for providing a second threshold voltage of the second transistor gate. The second threshold voltage is within a predetermined range of the first threshold voltage. Provide data relating to process adjustment to a process controller for performing the process adjustment.

公开(公告)号：US10325824B2

公开(公告)日：2019-06-18

申请号：US15622061

申请日：2017-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mitsuhiro Togo ,  Ram Asra ,  Xing Zhang ,  Palanivel Balasubramaniam

IPC: H01L21/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423

Abstract: At least one method, apparatus and system are disclosed for controlling threshold voltage values for a plurality of transistor devices. Determine a first threshold voltage of a first transistor gate comprising a first gate channel having a first length. Determine a second length of a second gate channel of a second transistor gate. Determining a process adjustment of the second gate based on the second length for providing a second threshold voltage of the second transistor gate. The second threshold voltage is within a predetermined range of the first threshold voltage. Provide data relating to process adjustment to a process controller for performing the process adjustment.

公开(公告)号：US09679990B2

公开(公告)日：2017-06-13

申请号：US14454778

申请日：2014-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edmund Kenneth Banghart ,  Mitsuhiro Togo ,  Shesh Mani Pandey

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.

公开(公告)号：US09362284B2

公开(公告)日：2016-06-07

申请号：US14924486

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro Togo ,  Changyong Xiao ,  Yiqun Liu ,  Dina H. Triyoso ,  Rohit Pal

IPC: H01L29/00 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/324 ,  H01L21/265 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.