公开(公告)号：US20180233415A1

公开(公告)日：2018-08-16

申请号：US15947479

申请日：2018-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani PANDEY ,  Baofu ZHU ,  Srikanth Balaji SAMAVEDAM

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/66818 ,  H01L29/7853

Abstract: A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.

公开(公告)号：US20160308005A1

公开(公告)日：2016-10-20

申请号：US15189079

申请日：2016-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie FENG ,  Jianwei PENG ,  Yanxiang LIU ,  Shesh Mani PANDEY ,  Francis BENISTANT

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/417 ,  H01L29/78 ,  H01L21/265 ,  H01L21/268 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/105 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.

Abstract translation: 公开了一种形成具有突然，垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在半导体鳍片上方并垂直于半导体鳍片形成栅电极; 在栅电极的相对侧上形成第一间隔物; 在所述翅片的相对侧上形成第二间隔物; 在第二间隔件之间形成邻近第一间隔件的翅片中的空腔; 在每个腔中部分地外延生长源/漏区; 将第一掺杂剂注入部分生长的源极/漏极区域中，其后可选择的RTA; 在空腔中外延生长源/漏区的剩余部分，原位掺杂有第二掺杂剂; 以及在源极/漏极区域中注入第三掺杂剂。

公开(公告)号：US20160043190A1

公开(公告)日：2016-02-11

申请号：US14454778

申请日：2014-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edmund Kenneth BANGHART ,  Mitsuhiro TOGO ,  Shesh Mani PANDEY

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.

Abstract translation: 提供半导体结构和制造方法，其中一个或两个扩展的源到沟道接口或延伸的漏极到沟道的接口。 制造方法包括例如使半导体材料凹陷以形成与正在制造的半导体结构的沟道区相邻的空腔，凹陷在空腔内形成第一空腔表面和第二空腔表面; 以及通过所述第一空腔表面将一种或多种掺杂剂注入所述半导体材料中以限定所述半导体材料内的注入区域，并且形成扩展的沟道界面，所述扩展沟道界面部分地包括所述半导体内的所述注入区域的界面 材料到半导体结构的沟道区域。 在一个实施例中，具有扩展通道接口的半导体结构是FinFET。

公开(公告)号：US20150311293A1

公开(公告)日：2015-10-29

申请号：US14259726

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shiv Kumar MISHRA ,  Zhiqing LI ,  Scott BEASOR ,  Shesh Mani PANDEY

IPC: H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/365 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/78

Abstract: P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are provided. The pMOSFET's include a silicon-germanium (SiGe) film that has a lower interface in contact with a semiconductor substrate and an upper surface, and the SiGe film has a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film. Methods of forming the pMOSFET's include: providing a semiconductor substrate; depositing a SiGe film on the semiconductor substrate, thereby forming a lower interface of the SiGe film in contact with the semiconductor substrate, and an upper surface of the SiGe film; and doping the SiGe film with boron to form a SiGe film having a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film.

Abstract translation: 提供了P型金属氧化物半导体场效应晶体管（pMOSFET），包括pMOSFET的半导体器件和形成pMOSFET的方法。 pMOSFET包括具有与半导体衬底和上表面接触的较低界面的硅 - 锗（SiGe）膜，并且SiGe膜具有梯度硼掺杂分布，其中硼含量在硼的宽度的大部分上向上增加 SiGe膜的下界面与SiGe膜的上表面之间的掺杂SiGe膜。 形成pMOSFET的方法包括：提供半导体衬底; 在半导体衬底上沉积SiGe膜，从而形成与半导体衬底接触的SiGe膜的下界面和SiGe膜的上表面; 并且用硼掺杂SiGe膜以形成具有渐变硼掺杂分布的SiGe膜，其中硼含量在SiGe膜的下界面和SiGe的上表面之间的硼掺杂SiGe膜的宽度的大部分上向上增加 电影。

公开(公告)号：US20170278965A1

公开(公告)日：2017-09-28

申请号：US15079142

申请日：2016-03-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani PANDEY ,  Pei ZHAO ,  Zhenyu HU

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods to reduce a width of a channel region of Si fins and the resulting devices are disclosed. Embodiments include forming a Si fin in a Si layer; forming a channel region over the Si fin including a dummy gate with a spacer on each side; forming S/D regions at opposite ends of the Si fin; removing the dummy gate, forming a cavity; thinning sidewalls of the Si fin; and forming a high-k/metal gate in the cavity.

公开(公告)号：US20170025270A1

公开(公告)日：2017-01-26

申请号：US14807289

申请日：2015-07-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar SINGH ,  Shesh Mani PANDEY

IPC: H01L21/02 ,  H01L21/308 ,  H01L27/08 ,  H01L21/283 ,  H01L49/02 ,  H01L21/3065 ,  H01L21/3105

CPC classification number: H01L23/5223 ,  H01L21/02186 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31051 ,  H01L23/53228 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/55

Abstract: A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench.

Abstract translation: 一种方法可以包括在半导体结构上施加图案化掩模，所述半导体结构具有电介质层，使用所述图案化掩模形成在所述电介质层中形成的第一和第二间隔开的金属结构之间的材料形成沟槽，以及设置电介质材料形成 在材料形成沟槽中。

公开(公告)号：US20190378763A1

公开(公告)日：2019-12-12

申请号：US16005073

申请日：2018-06-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Ruilong XIE ,  Shesh Mani PANDEY ,  Hui ZANG ,  Garo Jacques DERDERIAN ,  Scott BEASOR

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/308 ,  H01L21/762 ,  H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.

公开(公告)号：US20180040696A1

公开(公告)日：2018-02-08

申请号：US15227330

申请日：2016-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiqing LI ,  Shesh Mani PANDEY ,  Francis BENISTANT

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/22 ,  H01L29/167 ,  H01L29/16 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/2225 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming NFET S/D structures with multiple layers, with consecutive epi-SiP layers being doped at increasing dosages of P and the resulting device are provided. Embodiments include forming multiple epi-Si layers in each S/D cavity of a NFET; and performing in-situ doping of P for each epi-Si layer, wherein consecutive epi-Si layers are doped at increasing dosages of P.

公开(公告)号：US20170294378A1

公开(公告)日：2017-10-12

申请号：US15625035

申请日：2017-06-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar SINGH ,  Shesh Mani PANDEY

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L23/5223 ,  H01L21/02186 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31051 ,  H01L23/53228 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/55

Abstract: A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench.

公开(公告)号：US20170222054A1

公开(公告)日：2017-08-03

申请号：US15491465

申请日：2017-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edmund Kenneth BANGHART ,  Mitsuhiro TOGO ,  Shesh Mani PANDEY

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.