公开(公告)号：US09660030B2

公开(公告)日：2017-05-23

申请号：US14473033

申请日：2014-08-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shom Ponoth ,  Marc A. Bergendahl ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC: H01L29/165 ,  H01L21/338 ,  H01L29/08 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/0257 ,  H01L21/02636 ,  H01L21/28008 ,  H01L21/28114 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity.

公开(公告)号：US09373580B2

公开(公告)日：2016-06-21

申请号：US14140060

申请日：2013-12-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： John C. Arnold ,  Sean D. Burns ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian ,  Yunpeng Yin

IPC: H01L21/00 ,  H01L23/522 ,  G03F7/00 ,  G03F7/09 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L23/5226 ,  G03F7/0035 ,  G03F7/091 ,  G03F7/094 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L2924/0002 ,  Y10T428/24355 ,  H01L2924/00

Abstract: A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.

Abstract translation: 在互连级介质层上的第一金属硬掩模层用线图案图案化。 在第一金属硬掩模层上方施加至少一个介电材料层，第二金属硬掩模层，第一有机平坦化层（OPL）和第一光致抗蚀剂。 第一通孔图案从第一光致抗蚀剂层转移到第二金属硬掩模层中。 第二OPL和第二光致抗蚀剂被施加和图案化，第二通孔图案被转移到第二金属硬掩模层中。 第一和第二通孔图案的第一复合图案被转移到至少一个介电材料层中。 将第一复合图案与第一金属硬掩模层中的开口的面积限制的第二复合图案被转移到互连级介质层中。

公开(公告)号：US09356046B2

公开(公告)日：2016-05-31

申请号：US14088025

申请日：2013-11-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Ali Khakifirooz

IPC: H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092

CPC classification number: H01L27/1211 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924

Abstract: Embodiments of the present invention provide an improved structure and method for forming CMOS field effect transistors. In embodiments, silicon germanium (SiGe) is formed on a PFET side of a semiconductor structure, while silicon is disposed on an NFET side of a semiconductor structure. A narrow isolation region is formed between the PFET and NFET. The NFET fins are comprised of silicon and the PFET fins are comprised of silicon germanium.

Abstract translation: 本发明的实施例提供了一种用于形成CMOS场效应晶体管的改进的结构和方法。 在实施例中，在半导体结构的PFET侧形成硅锗（SiGe），而在半导体结构的NFET侧设置硅。 在PFET和NFET之间形成窄的隔离区。 NFET鳍由硅构成，PFET鳍由硅锗构成。

公开(公告)号：US09269621B2

公开(公告)日：2016-02-23

申请号：US14449314

申请日：2014-08-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/311 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

Abstract translation: 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 之后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的 第一条金属线。 形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

公开(公告)号：US09214397B2

公开(公告)日：2015-12-15

申请号：US13788689

申请日：2013-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kerber ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823842

Abstract: A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

Abstract translation: 一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离 存在于第二导电装置区域上的高k栅介质层。 连接栅极导体形成在高k栅介质层的第一部分和第二部分上。 连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。 然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。 用含氧气氛曝光改变暴露的半导体器件的阈值电压。

公开(公告)号：US09263388B2

公开(公告)日：2016-02-16

申请号：US14688027

申请日：2015-04-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L21/44

CPC classification number: H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.