摘要:
Methods and compositions are provided for the use of an envelope polypeptide or a functional variant thereof from a lentivirus that is not HIV-1 as a molecular scaffold for HIV-1 epitopes. The HIV-1 epitopes can be recognized by HIV-1 binding antibodies, HIV-1 neutralizing antibodies and/or CD4-induced antibodies. Thus, methods are provided for detecting HIV-1 binding antibodies in a subject infected with HTV-1. Further provided are methods to determine an epitope for an HIV-1 binding antibody; methods to assay for an HIV-1 binding antibody; methods to identify a soluble CD4 mimic; methods to neutralize an non-HIV-1 virus; diagnostic assays to monitor HIV disease in a subject or to monitor the subject's response to immunization by a HIV vaccine; and methods to alter the neutralization potential of an HIV-1 derived CD4-induced antibody. Chimeric polypeptides, chimeric polynucleotides, kits, cells and viruses are also provided.
摘要:
The present invention relates, in general, to an immunogen and, in particular, to an immunogen for inducing antibodies that neutralizes a wide spectrum of HIV primary isolates and/or to an immunogen that induces a T cell immune response. The invention also relates to a method of inducing anti-HIV antibodies, and/or to a method of inducing a T cell immune response, using such an immunogen. The invention further relates to nucleic acid sequences encoding the present immunogens.
摘要:
The nucleotide sequences of the genomes of eleven molecular clones for non-subtype B isolates of human immunodeficiency virus type 1 are disclosed. The invention relates to the nucleic acids and peptides encoded by and/or derived from these sequences and their use in diagnostic methods and as immunogens.
摘要:
Resource management architectures implemented in computer systems to manage resources are described. In one embodiment, a general architecture includes a resource manager and multiple resource providers that support one or more resource consumers such as a system component or application. Each provider is associated with a resource and acts as the manager for the resource when interfacing with the resource manager. The resource manager arbitrates access to the resources provided by the resource providers on behalf of the consumers. A policy manager sets various policies that are used by the resource manager to allocate resources. One policy is a priority-based policy that distinguishes among which applications and/or users have priority over others to use the resources. A resource consumer creates an “activity” at the resource manager and builds one or more “configurations” that describe various sets of preferred resources required to perform the activity. Each resource consumer can specify one or more configurations for each activity. If multiple configurations are specified, the resource consumer can rank them according to preference. This allows the resource consumers to be dynamically changed from one configuration to another as operating conditions change.
摘要:
A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.
摘要:
A space is modeled using images from a set of cameras in the space. An easy to use tool is provided that allows users to identify a reference location in an image and a corresponding reference location on a floor plan of the space. Based on these correspondences, a model is generated that can map a point in a camera's view to a point on the floor plan, or vice-versa. Subjects moving through the space are identified and tracked using the model and attributes associated with a subject. In a specific implementation, the attributes include velocity, color, size, and position. In a specific implementation, the space is a retail store and the subjects are customers browsing through the retail store.
摘要:
In one embodiment, a neurological status evaluation apparatus includes a signal generator configured to generate an electromagnetic signal at one or more frequencies, a transmitting antenna coupled to the signal generator and configure to transmit the electromagnetic signal, and a receiving antenna positioned proximate to the transmitting antenna such that an evaluation space is defined between the transmitting antenna and the receiving antenna. The biological tissue under evaluation does not contact the transmitting antenna or the receiving antenna. The receiving antenna receives a modulated electromagnetic signal after propagating through the biological tissue under evaluation. The neurological status evaluation apparatus further includes a spectrum analyzer coupled to the receiving antenna, wherein the spectrum analyzer receives and samples the modulated electromagnetic signal. A computing device is coupled to the spectrum analyzer, calculates an evaluation, and provides a neurological status indicator of the biological tissue under evaluation based on the evaluation parameter.
摘要:
In one embodiment, a neurological status evaluation apparatus includes a signal generator configured to generate an electromagnetic signal at one or more frequencies, a transmitting antenna coupled to the signal generator and configure to transmit the electromagnetic signal, and a receiving antenna positioned proximate to the transmitting antenna such that an evaluation space is defined between the transmitting antenna and the receiving antenna. The biological tissue under evaluation does not contact the transmitting antenna or the receiving antenna. The receiving antenna receives a modulated electromagnetic signal after propagating through the biological tissue under evaluation. The neurological status evaluation apparatus further includes a spectrum analyzer coupled to the receiving antenna, wherein the spectrum analyzer receives and samples the modulated electromagnetic signal. A computing device is coupled to the spectrum analyzer, calculates an evaluation, and provides a neurological status indicator of the biological tissue under evaluation based on the evaluation parameter.
摘要:
A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.
摘要:
An interactive video system is provided that is capable of combining streaming televised events with video conferencing technology to create a social television experience. A first user is able to connect via a webcam and microphone to a server that combines the webcam video and sound from the microphone with a streaming video that could be a televised event. The combined webcam video, microphone sound, and streaming video is then broadcast to the first user and other users such that the users are capable of viewing the streaming video with the live conferencing video and sound from the first user. This procedure may be repeated such that a plurality of users may video conference live on top of the streaming video.