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    Molecular Scaffolds for HIV-1 Epitopes
    1.
    发明申请
    Molecular Scaffolds for HIV-1 Epitopes 失效
    HIV-1表位的分子支架

    公开(公告)号：US20080096187A1

    公开(公告)日：2008-04-24

    申请号：US11578761

    申请日：2005-04-08

    申请人： George Shaw ,  James Robinson ,  Frederic Bibollet-Ruche ,  Julie Decker ,  Beatrice Hahn

    发明人： George Shaw ,  James Robinson ,  Frederic Bibollet-Ruche ,  Julie Decker ,  Beatrice Hahn

    IPC分类号： C07H21/04 ,  C07K16/00 ,  C12N5/00 ,  C12N7/00 ,  C12Q1/70

    CPC分类号： G01N33/56988 ,  C07K16/1063 ,  C07K16/2812 ,  C07K2317/32 ,  C07K2317/34 ,  C07K2317/76 ,  G01N2469/20

    摘要： Methods and compositions are provided for the use of an envelope polypeptide or a functional variant thereof from a lentivirus that is not HIV-1 as a molecular scaffold for HIV-1 epitopes. The HIV-1 epitopes can be recognized by HIV-1 binding antibodies, HIV-1 neutralizing antibodies and/or CD4-induced antibodies. Thus, methods are provided for detecting HIV-1 binding antibodies in a subject infected with HTV-1. Further provided are methods to determine an epitope for an HIV-1 binding antibody; methods to assay for an HIV-1 binding antibody; methods to identify a soluble CD4 mimic; methods to neutralize an non-HIV-1 virus; diagnostic assays to monitor HIV disease in a subject or to monitor the subject's response to immunization by a HIV vaccine; and methods to alter the neutralization potential of an HIV-1 derived CD4-induced antibody. Chimeric polypeptides, chimeric polynucleotides, kits, cells and viruses are also provided.

    摘要翻译： 提供了使用来自不是HIV-1作为HIV-1表位的分子支架的慢病毒的包膜多肽或其功能变体的方法和组合物。 HIV-1表位可被HIV-1结合抗体，HIV-1中和抗体和/或CD4诱导的抗体识别。 因此，提供了用于检测感染HTV-1的受试者中的HIV-1结合抗体的方法。 还提供了确定HIV-1结合抗体的表位的方法; 测定HIV-1结合抗体的方法; 识别可溶性CD4模拟物的方法; 中和非HIV-1病毒的方法; 用于监测受试者中艾滋病病毒的诊断测定或监测受试者对HIV疫苗免疫接种的反应; 以及改变HIV-1衍生的CD4诱导抗体的中和电位的方法。 还提供了嵌合多肽，嵌合多核苷酸，试剂盒，细胞和病毒。

    Resource manager architecture
    4.
    发明授权
    Resource manager architecture 有权
    资源管理器架构

    公开(公告)号：US07337446B2

    公开(公告)日：2008-02-26

    申请号：US10931058

    申请日：2004-08-31

    申请人： Mukund Sankaranarayan ,  Forrest C. Foltz ,  George Shaw ,  Dale A. Sather ,  Andy R. Raffman ,  Jai Srinivasan ,  Terje K. Backman ,  William G. Parry ,  David S. Bakin ,  Michael B. Jones ,  Sean C. McDowell ,  Jayachandran Raja ,  Robin Speed

    发明人： Mukund Sankaranarayan ,  Forrest C. Foltz ,  George Shaw ,  Dale A. Sather ,  Andy R. Raffman ,  Jai Srinivasan ,  Terje K. Backman ,  William G. Parry ,  David S. Bakin ,  Michael B. Jones ,  Sean C. McDowell ,  Jayachandran Raja ,  Robin Speed

    IPC分类号： G06F9/46 ,  G06F15/16

    CPC分类号： G06F9/50 ,  G06F9/526 ,  G06F2209/5014 ,  G06F2209/522 ,  H04N21/4424 ,  H04N21/443

    摘要： Resource management architectures implemented in computer systems to manage resources are described. In one embodiment, a general architecture includes a resource manager and multiple resource providers that support one or more resource consumers such as a system component or application. Each provider is associated with a resource and acts as the manager for the resource when interfacing with the resource manager. The resource manager arbitrates access to the resources provided by the resource providers on behalf of the consumers. A policy manager sets various policies that are used by the resource manager to allocate resources. One policy is a priority-based policy that distinguishes among which applications and/or users have priority over others to use the resources. A resource consumer creates an “activity” at the resource manager and builds one or more “configurations” that describe various sets of preferred resources required to perform the activity. Each resource consumer can specify one or more configurations for each activity. If multiple configurations are specified, the resource consumer can rank them according to preference. This allows the resource consumers to be dynamically changed from one configuration to another as operating conditions change.

    摘要翻译： 描述了在计算机系统中实现的管理资源的资源管理架构。 在一个实施例中，一般架构包括资源管理器和支持一个或多个资源消费者（诸如系统组件或应用程序）的多个资源提供者。 当与资源管理器进行接口时，每个提供者都与资源相关联并充当该资源的管理器。 资源管理员代表消费者对资源提供者提供的资源的访问进行仲裁。 策略管理器设置资源管理器使用的各种策略来分配资源。 一个策略是一个基于优先级的策略，区分哪些应用程序和/或用户优先于其他应用程序和/或用户来使用资源。 资源消费者在资源管理器中创建“活动”，并构建一个或多个描述执行活动所需的各种首选资源集的“配置”。 每个资源消费者可以为每个活动指定一个或多个配置。 如果指定了多个配置，资源消费者可以根据喜好对其进行排名。 这允许在操作条件改变时资源消费者从一个配置动态地改变另一个配置。

    Availability of space in a RISC microprocessor architecture
    5.
    发明申请
    Availability of space in a RISC microprocessor architecture 审中-公开
    RISC微处理器架构中空间的可用性

    公开(公告)号：US20070271441A1

    公开(公告)日：2007-11-22

    申请号：US11881283

    申请日：2007-07-26

    申请人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

    发明人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

    IPC分类号： G06F15/00

    CPC分类号： G06F12/0875 ,  G06F9/30014 ,  G06F9/3005 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/126

    摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

    摘要翻译： 微处理器以100 MHz内部时钟频率执行100个本机MIPS峰值性能。 中央处理单元（CPU）指令集是硬连线的，允许大多数指令在一个周期内执行。 “流通”设计允许下一条指令在先前指令完成之前启动，从而提高性能。 微处理单元（MPU）包含52个通用寄存器，包括16个全局数据寄存器，一个索引寄存器，一个计数寄存器，一个16深可寻址寄存器/返回堆栈以及一个18深操作数堆栈。 两个堆栈都包含顶部元素中的索引寄存器，缓存在芯片上，并在需要时自动溢出并从外部存储器中重新填充。 堆栈最小化数据移动，并在过程调用，参数传递和变量赋值期间最小化存储器访问。 此外，MPU还包含一个模式/状态寄存器和41个用于I / O，控制，配置和状态的本地寻址寄存器。 CPU包含高性能零操作数双堆栈架构MPU和执行指令传输数据，计数事件，测量时间和执行其他与时序相关的功能的输入输出处理器（IOP）。 零操作数堆栈架构消除了操作数位。 堆栈还可以在过程内和跨过程中最小化寄存器保存和加载，从而允许较短的指令序列和更快的运行代码。 指令简单易于解码和执行，允许MPU和IOP在单个时钟周期内发出和完成指令，每个时钟周期为100个本机MIPS峰值执行。 每次执行指令提取或预取时，CPU使用8位操作码，最多可从内存中获取四条指令。 这些指令可以重复，而不会从内存重新读取。 当直接连接到DRAM而没有高速缓存时，这将保持高性能。

    Method and system for full path analysis
    6.
    发明授权
    Method and system for full path analysis 有权

    公开(公告)号：US10163031B2

    公开(公告)日：2018-12-25

    申请号：US13603832

    申请日：2012-09-05

    申请人： George Shaw

    发明人： George Shaw

    IPC分类号： G06K9/60 ,  G06K9/00

    摘要： A space is modeled using images from a set of cameras in the space. An easy to use tool is provided that allows users to identify a reference location in an image and a corresponding reference location on a floor plan of the space. Based on these correspondences, a model is generated that can map a point in a camera's view to a point on the floor plan, or vice-versa. Subjects moving through the space are identified and tracked using the model and attributes associated with a subject. In a specific implementation, the attributes include velocity, color, size, and position. In a specific implementation, the space is a retail store and the subjects are customers browsing through the retail store.

    Apparatuses and methods for neurological status evaluation using electromagnetic signals
    7.
    发明授权
    Apparatuses and methods for neurological status evaluation using electromagnetic signals 有权
    使用电磁信号进行神经状态评估的装置和方法

    公开(公告)号：US09357970B2

    公开(公告)日：2016-06-07

    申请号：US13977689

    申请日：2011-12-30

    申请人： Joseph Floyd Clark ,  Matthew L. Flaherty ,  George Shaw ,  Opeolu Adeoye

    发明人： Joseph Floyd Clark ,  Matthew L. Flaherty ,  George Shaw ,  Opeolu Adeoye

    IPC分类号： A61B5/05 ,  A61B5/00 ,  A61B5/04 ,  A61B5/02

    CPC分类号： A61B5/04008 ,  A61B5/0042 ,  A61B5/0075 ,  A61B5/02042 ,  A61B5/04001 ,  A61B5/4064 ,  A61B5/4094 ,  A61B5/4878 ,  A61B5/6803 ,  A61B5/7225 ,  A61B5/7257 ,  A61B5/7282 ,  A61B5/742 ,  A61B5/746 ,  A61B2562/0223 ,  A61B2576/026

    摘要： In one embodiment, a neurological status evaluation apparatus includes a signal generator configured to generate an electromagnetic signal at one or more frequencies, a transmitting antenna coupled to the signal generator and configure to transmit the electromagnetic signal, and a receiving antenna positioned proximate to the transmitting antenna such that an evaluation space is defined between the transmitting antenna and the receiving antenna. The biological tissue under evaluation does not contact the transmitting antenna or the receiving antenna. The receiving antenna receives a modulated electromagnetic signal after propagating through the biological tissue under evaluation. The neurological status evaluation apparatus further includes a spectrum analyzer coupled to the receiving antenna, wherein the spectrum analyzer receives and samples the modulated electromagnetic signal. A computing device is coupled to the spectrum analyzer, calculates an evaluation, and provides a neurological status indicator of the biological tissue under evaluation based on the evaluation parameter.

    摘要翻译： 在一个实施例中，神经状态评估装置包括被配置为产生一个或多个频率的电磁信号的信号发生器，耦合到信号发生器并被配置为传送电磁信号的发射天线以及靠近发射 天线，使得在发射天线和接收天线之间定义评估空间。 所评估的生物组织不接触发射天线或接收天线。 接收天线在评估后通过生物组织传播后接收调制电磁信号。 神经状态评估装置还包括耦合到接收天线的频谱分析仪，其中频谱分析仪接收并采样调制的电磁信号。 计算设备耦合到频谱分析仪，计算评估，并根据评估参数提供正在评估的生物组织的神经状态指标。

    Apparatuses and methods for neurological status evaluation using electromagnetic signals
    8.
    发明授权
    Apparatuses and methods for neurological status evaluation using electromagnetic signals 有权

    公开(公告)号：US09320472B2

    公开(公告)日：2016-04-26

    申请号：US13977689

    申请日：2011-12-30

    申请人： Joseph Floyd Clark ,  Matthew L. Flaherty ,  George Shaw ,  Opeolu Adeoye

    发明人： Joseph Floyd Clark ,  Matthew L. Flaherty ,  George Shaw ,  Opeolu Adeoye

    IPC分类号： A61B5/05 ,  A61B5/00 ,  A61B5/04 ,  A61B5/02

    摘要： In one embodiment, a neurological status evaluation apparatus includes a signal generator configured to generate an electromagnetic signal at one or more frequencies, a transmitting antenna coupled to the signal generator and configure to transmit the electromagnetic signal, and a receiving antenna positioned proximate to the transmitting antenna such that an evaluation space is defined between the transmitting antenna and the receiving antenna. The biological tissue under evaluation does not contact the transmitting antenna or the receiving antenna. The receiving antenna receives a modulated electromagnetic signal after propagating through the biological tissue under evaluation. The neurological status evaluation apparatus further includes a spectrum analyzer coupled to the receiving antenna, wherein the spectrum analyzer receives and samples the modulated electromagnetic signal. A computing device is coupled to the spectrum analyzer, calculates an evaluation, and provides a neurological status indicator of the biological tissue under evaluation based on the evaluation parameter.

    Floating point exception handling in a risc microprocessor architecture
    9.
    发明申请
    Floating point exception handling in a risc microprocessor architecture 审中-公开

    公开(公告)号：US20080072021A1

    公开(公告)日：2008-03-20

    申请号：US11981453

    申请日：2007-10-31

    申请人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

    发明人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

    IPC分类号： G06F9/302

    CPC分类号： G06F12/0875 ,  G06F9/30014 ,  G06F9/3005 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/126

    摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

    INTERACTIVE VIDEO SYSTEM
    10.
    发明申请
    INTERACTIVE VIDEO SYSTEM 有权
    互动视频系统

    公开(公告)号：US20110145881A1

    公开(公告)日：2011-06-16

    申请号：US12962529

    申请日：2010-12-07

    申请人： Anthony Hartman ,  George Shaw

    发明人： Anthony Hartman ,  George Shaw

    IPC分类号： H04N7/173

    CPC分类号： H04N21/4788 ,  H04N7/15 ,  H04N21/42203 ,  H04N21/4223 ,  H04N21/4438 ,  H04N21/4755

    摘要： An interactive video system is provided that is capable of combining streaming televised events with video conferencing technology to create a social television experience. A first user is able to connect via a webcam and microphone to a server that combines the webcam video and sound from the microphone with a streaming video that could be a televised event. The combined webcam video, microphone sound, and streaming video is then broadcast to the first user and other users such that the users are capable of viewing the streaming video with the live conferencing video and sound from the first user. This procedure may be repeated such that a plurality of users may video conference live on top of the streaming video.

    摘要翻译： 提供了一种交互式视频系统，其能够将流媒体电视事件与视频会议技术相结合，以创建社交电视体验。 第一个用户能够通过网络摄像头和麦克风连接到将麦克风的网络摄像头视频和声音与可以是电视转播事件的流式视频相结合的服务器。 然后将组合的网络摄像头视频，麦克风声音和流视频广播到第一用户和其他用户，使得用户能够使用来自第一用户的现场会议视频和声音来观看流式视频。 可以重复该过程，使得多个用户可以在流式视频的顶部上进行视频会议。