公开(公告)号：US20110193215A1

公开(公告)日：2011-08-11

申请号：US13023565

申请日：2011-02-09

申请人： Masahiro TOYAMA ,  Yutaka UEMATSU ,  Hideki OSAKA

发明人： Masahiro TOYAMA ,  Yutaka UEMATSU ,  Hideki OSAKA

IPC分类号： H01L23/50

CPC分类号： H01L23/50 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49112 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00

摘要： Means for decreasing parasitic inductance by a realistic mounting method is provided. On a surface layer of a semiconductor package, there is provided a ground pad having a plurality of comb-tooth-shaped ground pads which are connecting points for wire bonding and are protruded on the surface layer of the semiconductor package. A power-supply pad is arranged between the comb-tooth-shaped ground pads. Two long and short ground wires are arranged in one comb-tooth-shaped ground pad. Also, two long and short power-supply wires are arranged in one power-supply pad. By arranging the long ground wire and the long power-supply wire so as to be parallel and close to each other and arranging the short power-supply wire and the short ground wire so as to be parallel and close to each other, the parasitic inductance is decreased.

摘要翻译： 提供了通过现实的安装方法来减小寄生电感的方法。 在半导体封装的表面层上，设置有多个梳齿形接地焊盘的接地焊盘，这些接地焊盘是用于引线接合的连接点，并且突出在半导体封装的表面层上。 在梳齿形接地垫之间设置电源垫。 两根长而短的接地线布置在一个梳齿形接地垫中。 此外，两个长短电源线布置在一个电源垫中。 通过将长接地线和长电源线布置为彼此并联并且将短电源线和短接地线布置成彼此并联并且彼此靠近，寄生电感 减少。

公开(公告)号：US20110239176A1

公开(公告)日：2011-09-29

申请号：US13155204

申请日：2011-06-07

申请人： Hideki OSAKA ,  Yutaka UEMATSU

发明人： Hideki OSAKA ,  Yutaka UEMATSU

IPC分类号： G06F17/50

CPC分类号： H05K3/0005 ,  H05K1/0231 ,  H05K2201/093

摘要： An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

摘要翻译： 仅通过执行电磁场分析一次形成正交阵列，并且通过使用电容器的安装位置和类型以及电容器数量作为参数来确定范围以进行电路分析次数少。 通过使用计算的电源阻抗的绝对值的结果作为指标来形成估计方程，并且通过使用估计方程来设置电容器以减少噪声。

公开(公告)号：US20110234249A1

公开(公告)日：2011-09-29

申请号：US13044717

申请日：2011-03-10

申请人： Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

发明人： Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

IPC分类号： G01R31/00

CPC分类号： G01R31/2889

摘要： An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

摘要翻译： 安装有作为测试对象的集成电路的插入器设置有用于检测与集成电路的各个端子相对应的电流的开关和探头。 然后，通过作为与集成电路的电源端子连接并断开的开关的测试基板将测试图形信号输入到集成电路。 如果集成电路正常工作，并且集成电路的所有端子的电流值都在容差内，则连接到关断开关的电源端子被识别为可以被去除的端子。

公开(公告)号：US20090213558A1

公开(公告)日：2009-08-27

申请号：US12361761

申请日：2009-01-29

申请人： Hideki OSAKA ,  Yutaka Uematsu

发明人： Hideki OSAKA ,  Yutaka Uematsu

IPC分类号： H05K1/18

CPC分类号： H05K3/0005 ,  H05K1/0231 ,  H05K2201/093

摘要： An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

摘要翻译： 仅通过执行电磁场分析一次形成正交阵列，并且通过使用电容器的安装位置和类型以及电容器数量作为参数来确定范围以进行电路分析次数少。 通过使用计算的电源阻抗的绝对值的结果作为指标来形成估计方程，并且通过使用估计方程来设置电容器以减少噪声。

公开(公告)号：US20070291557A1

公开(公告)日：2007-12-20

申请号：US11761470

申请日：2007-06-12

申请人： Yoji NISHIO ,  Yutaka UEMATSU ,  Seiji FUNABA ,  Hideki OSAKA ,  Tsutomu HARA ,  Koichiro AOKI

发明人： Yoji NISHIO ,  Yutaka UEMATSU ,  Seiji FUNABA ,  Hideki OSAKA ,  Tsutomu HARA ,  Koichiro AOKI

IPC分类号： G11C5/06 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/02 ,  G11C5/02 ,  G11C5/04 ,  H01L25/105 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

摘要： Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.

摘要翻译： 堆叠的半导体器件包括堆叠在一起的多个存储器芯片，其中高速传输中的波形失真被去除。 堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。 作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。 数据选通信号和反相数据选通信号相互配合。 用于数据选通信号L 4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于DQS信号L 5的反相数据选通信号线连接到反相数据选通信号（/ DQS）焊盘 的第二存储器芯片12。

公开(公告)号：US20080258259A1

公开(公告)日：2008-10-23

申请号：US12107758

申请日：2008-04-22

申请人： Hideki OSAKA ,  Tatsuya Saito

发明人： Hideki OSAKA ,  Tatsuya Saito

IPC分类号： H01L45/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/50 ,  H01L23/642 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S257/904 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor chip and a semiconductor device mounting the semiconductor chip capable of increasing a capacitance of a capacitor without reducing the number of signal bumps or power bumps of a package and the number of C4 solder balls of the semiconductor chip, and achieving a stable power supply with suppressing fluctuations of power at a resonance frequency without a limitation in a position to mount a capacitor for lowering noise of a signal transceiving interface block. In the semiconductor device, a via hole is provided to the semiconductor chip, a power-supply electrode connected to the via hole is provided to a back surface of the semiconductor chip, and a capacitor is mounted to the electrode on the back surface. And, a high-resistance material is used for a material of a power-supply via hole inside the semiconductor chip, thereby increasing the resistance and lowering the Q factor.

摘要翻译： 一种半导体芯片和半导体器件，其安装半导体芯片能够增加电容器的电容而不减少封装的信号凸块或功率凸块的数量以及半导体芯片的C 4焊球的数量，并且实现稳定的功率 在谐振频率下抑制功率波动而不受限于安装用于降低信号收发接口块噪声的电容器的位置。 在半导体装置中，在半导体芯片上设置有通孔，在该半导体芯片的背面设有与通路孔连接的电源电极，在背面的电极上安装有电容器。 并且，高电阻材料用于半导体芯片内的电源通孔的材料，从而增加电阻并降低Q因子。