公开(公告)号：US20070291557A1

公开(公告)日：2007-12-20

申请号：US11761470

申请日：2007-06-12

申请人： Yoji NISHIO ,  Yutaka UEMATSU ,  Seiji FUNABA ,  Hideki OSAKA ,  Tsutomu HARA ,  Koichiro AOKI

发明人： Yoji NISHIO ,  Yutaka UEMATSU ,  Seiji FUNABA ,  Hideki OSAKA ,  Tsutomu HARA ,  Koichiro AOKI

IPC分类号： G11C5/06 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/02 ,  G11C5/02 ,  G11C5/04 ,  H01L25/105 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

摘要： Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.

摘要翻译： 堆叠的半导体器件包括堆叠在一起的多个存储器芯片，其中高速传输中的波形失真被去除。 堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。 作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。 数据选通信号和反相数据选通信号相互配合。 用于数据选通信号L 4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于DQS信号L 5的反相数据选通信号线连接到反相数据选通信号（/ DQS）焊盘 的第二存储器芯片12。

公开(公告)号：US20110239176A1

公开(公告)日：2011-09-29

申请号：US13155204

申请日：2011-06-07

申请人： Hideki OSAKA ,  Yutaka UEMATSU

发明人： Hideki OSAKA ,  Yutaka UEMATSU

IPC分类号： G06F17/50

CPC分类号： H05K3/0005 ,  H05K1/0231 ,  H05K2201/093

摘要： An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

摘要翻译： 仅通过执行电磁场分析一次形成正交阵列，并且通过使用电容器的安装位置和类型以及电容器数量作为参数来确定范围以进行电路分析次数少。 通过使用计算的电源阻抗的绝对值的结果作为指标来形成估计方程，并且通过使用估计方程来设置电容器以减少噪声。

公开(公告)号：US20110234249A1

公开(公告)日：2011-09-29

申请号：US13044717

申请日：2011-03-10

申请人： Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

发明人： Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

IPC分类号： G01R31/00

CPC分类号： G01R31/2889

摘要： An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

摘要翻译： 安装有作为测试对象的集成电路的插入器设置有用于检测与集成电路的各个端子相对应的电流的开关和探头。 然后，通过作为与集成电路的电源端子连接并断开的开关的测试基板将测试图形信号输入到集成电路。 如果集成电路正常工作，并且集成电路的所有端子的电流值都在容差内，则连接到关断开关的电源端子被识别为可以被去除的端子。

公开(公告)号：US20080266031A1

公开(公告)日：2008-10-30

申请号：US12060941

申请日：2008-04-02

申请人： Yutaka UEMATSU ,  Hideki Osaka ,  Yoji Nishio ,  Eiichi Suzuki

发明人： Yutaka UEMATSU ,  Hideki Osaka ,  Yoji Nishio ,  Eiichi Suzuki

IPC分类号： H01P1/00

CPC分类号： H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/111 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/10734 ,  H01L2924/00

摘要： A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 μm therebetween.

摘要翻译： 提供了能够实现半导体器件的安装密度和噪声降低的改进的技术。 安装在印刷电路板上的LSI包括接地BGA球和电源BGA球，以从印刷线路板获得电源，并且接地BGA球和电源BGA球彼此靠近地布置。 去耦电容器安装在印刷电路板上，并具有第一端子和第二端子。 接地BGA球和第一端子通过第一金属电极板连接，电力BGA球和第二端子通过第二金属电极板连接。 第一金属电极板和第二金属电极板在其间插入厚度等于或小于1μm的电介质膜。

公开(公告)号：US20110193215A1

公开(公告)日：2011-08-11

申请号：US13023565

申请日：2011-02-09

申请人： Masahiro TOYAMA ,  Yutaka UEMATSU ,  Hideki OSAKA

发明人： Masahiro TOYAMA ,  Yutaka UEMATSU ,  Hideki OSAKA

IPC分类号： H01L23/50

CPC分类号： H01L23/50 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49112 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00

摘要： Means for decreasing parasitic inductance by a realistic mounting method is provided. On a surface layer of a semiconductor package, there is provided a ground pad having a plurality of comb-tooth-shaped ground pads which are connecting points for wire bonding and are protruded on the surface layer of the semiconductor package. A power-supply pad is arranged between the comb-tooth-shaped ground pads. Two long and short ground wires are arranged in one comb-tooth-shaped ground pad. Also, two long and short power-supply wires are arranged in one power-supply pad. By arranging the long ground wire and the long power-supply wire so as to be parallel and close to each other and arranging the short power-supply wire and the short ground wire so as to be parallel and close to each other, the parasitic inductance is decreased.

摘要翻译： 提供了通过现实的安装方法来减小寄生电感的方法。 在半导体封装的表面层上，设置有多个梳齿形接地焊盘的接地焊盘，这些接地焊盘是用于引线接合的连接点，并且突出在半导体封装的表面层上。 在梳齿形接地垫之间设置电源垫。 两根长而短的接地线布置在一个梳齿形接地垫中。 此外，两个长短电源线布置在一个电源垫中。 通过将长接地线和长电源线布置为彼此并联并且将短电源线和短接地线布置成彼此并联并且彼此靠近，寄生电感 减少。

公开(公告)号：US20120112849A1

公开(公告)日：2012-05-10

申请号：US13004609

申请日：2011-01-11

申请人： Yasuhiro IKEDA ,  Yutaka UEMATSU ,  Satoshi MURAOKA

发明人： Yasuhiro IKEDA ,  Yutaka UEMATSU ,  Satoshi MURAOKA

IPC分类号： H03H2/00 ,  H03H7/38

CPC分类号： H04B3/02

摘要： A data transmission system is provided in which it is possible to perform both of suppressing the degrading of the slew rate and suppressing the ringing even if load capacitance of an input buffer is changed.The data transmission system transmitting data from an output buffer to the input buffer through a trace is provided with first RC parallel circuits connected in series to the trace on a first Printed Circuit Board (PCB) on which the output buffer is mounted, and second RC parallel circuits connected in series to the trace on a second Printed Circuit Board (PCB) on which the input buffer is mounted, and which can be connected and separated to and from the first Printed Circuit Board (PCB).

摘要翻译： 提供了一种数据传输系统，其中即使输入缓冲器的负载电容改变，也可以同时执行抑制转换速率的降级和抑制振铃的两者。 通过轨迹将数据从输出缓冲器传输到输入缓冲器的数据传输系统提供有与其上安装有输出缓冲器的第一印刷电路板（PCB）上的迹线串联连接的第一RC并联电路，以及第二RC 并联电路与安装有输入缓冲器的第二印刷电路板（PCB）上的迹线串联连接，并且可以与第一个印刷电路板（PCB）连接和分离。

公开(公告)号：US20100090325A1

公开(公告)日：2010-04-15

申请号：US12576672

申请日：2009-10-09

申请人： Yutaka UEMATSU ,  Yukitoshi HIROSE

发明人： Yutaka UEMATSU ,  Yukitoshi HIROSE

IPC分类号： H01L25/16

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In order to solve a problem of increased noise accompanying increased area of a return path in a stacked package structure, provided is a semiconductor device which is formed in a stacked package such as a PoP package, which realizes low noise without changing a package size. An additional power supply wiring that runs along a signal wiring between an upper PoP and a lower PoP is newly added in the lower PoP of a package having a PoP structure.

摘要翻译： 为了解决伴随层叠封装结构中返回路径的面积增加的噪音增加的问题，提供了形成为诸如PoP封装的堆叠封装的半导体器件，其在不改变封装尺寸的情况下实现低噪声。 在具有PoP结构的封装的下部PoP中新添加沿着上部PoP和下部PoP之间的信号布线延伸的附加电源布线。