公开(公告)号：US07609572B2

公开(公告)日：2009-10-27

申请号：US11963831

申请日：2007-12-22

申请人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

发明人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C2207/005

摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

摘要翻译： 在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。 通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低 感觉速度增加。 因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

公开(公告)号：US20080181026A1

公开(公告)日：2008-07-31

申请号：US11963831

申请日：2007-12-22

申请人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

发明人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

IPC分类号： G11C7/08

CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C2207/005

摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

摘要翻译： 在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。 通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低 感觉速度增加。 因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

公开(公告)号：US07633833B2

公开(公告)日：2009-12-15

申请号：US12028788

申请日：2008-02-09

申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Satoru Akiyama ,  Hiroaki Nakaya ,  Masayuki Nakamura

发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Satoru Akiyama ,  Hiroaki Nakaya ,  Masayuki Nakamura

IPC分类号： G11C8/00

CPC分类号： G11C7/04 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2272

摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.

摘要翻译： 根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟 被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。 控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。

公开(公告)号：US20080239865A1

公开(公告)日：2008-10-02

申请号：US12028788

申请日：2008-02-09

申请人： Riichiro TAKEMURA ,  Tomonori Sekiguchi ,  Satoru Akiyama ,  Hiroaki Nakaya ,  Masayuki Nakamura

发明人： Riichiro TAKEMURA ,  Tomonori Sekiguchi ,  Satoru Akiyama ,  Hiroaki Nakaya ,  Masayuki Nakamura

IPC分类号： G11C8/00

CPC分类号： G11C7/04 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2272

摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.

摘要翻译： 根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟 被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。 控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。

公开(公告)号：US20080017904A1

公开(公告)日：2008-01-24

申请号：US11773990

申请日：2007-07-06

申请人： Satoru AKIYAMA ,  Ryuta Tsuchiya ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Masayuki Nakamura ,  Yasushi Yamazaki ,  Shigeru Shiratake

发明人： Satoru AKIYAMA ,  Ryuta Tsuchiya ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Masayuki Nakamura ,  Yasushi Yamazaki ,  Shigeru Shiratake

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

摘要： A DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability is provided. A gate electrode configuring a memory cell transistor of the DRAM is composed of an n-type polysilicon film and a W (tungsten) film stacked thereon. A part of the polysilicon film is embedded in a trench formed in a silicon substrate in order to elongate the effective channel length of the memory cell transistor. The other part of the polysilicon film is located above the trench, and an upper surface thereof is located above a surface of the silicon substrate (p-type well). Therefore, distances between the W film and a source and drain (n-type semiconductor regions) are ensured.

摘要翻译： 提供了能够实现降低功耗，高速运行和高可靠性的DRAM。 构成DRAM的存储单元晶体管的栅电极由n型多晶硅膜和堆叠在其上的W（钨）膜构成。 为了延长存储单元晶体管的有效沟道长度，多晶硅膜的一部分嵌入在硅衬底中形成的沟槽中。 多晶硅膜的另一部分位于沟槽上方，其上表面位于硅衬底的表面上方（p型阱）。 因此，确保W膜与源极和漏极（n型半导体区域）之间的距离。

公开(公告)号：US06538945B2

公开(公告)日：2003-03-25

申请号：US10050561

申请日：2002-01-18

申请人： Riichiro Takemura ,  Tsugio Takahashi ,  Masayuki Nakamura ,  Ryo Nagai ,  Norikatsu Takaura ,  Tomonori Sekiguchi ,  Shinichiro Kimura

发明人： Riichiro Takemura ,  Tsugio Takahashi ,  Masayuki Nakamura ,  Ryo Nagai ,  Norikatsu Takaura ,  Tomonori Sekiguchi ,  Shinichiro Kimura

IPC分类号： G11C700

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/10897

摘要： Providing a semiconductor device which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers. In a DRAM chip, P+-type gate PMOSs of P+-type polysilicon gates each having a low impurity density of channel and N+-type gate NMOSs of N+-type polysilicon gates are used in a sense amplifier cross coupling section to further increase substrate voltages of the PMOSs and to decrease substrate voltages of the NMOS. For this reason, a deviation of threshold voltage caused by channel implantation is reduced, and a small signal generated on a data line at a read operation of a low-potential memory array is accurately sensed and amplified by a sense amplifier. In addition, the threshold voltages are increased by a substrate bias effect, and a leakage current in a sense amplifier data holding state is reduced.

公开(公告)号：US5905685A

公开(公告)日：1999-05-18

申请号：US951734

申请日：1997-10-15

申请人： Masayuki Nakamura ,  Masatoshi Hasegawa ,  Seiji Narui ,  Yousuke Tanaka ,  Shinichi Miyatake ,  Shuichi Kubouchi ,  Kazuhiko Kajigaya

发明人： Masayuki Nakamura ,  Masatoshi Hasegawa ,  Seiji Narui ,  Yousuke Tanaka ,  Shinichi Miyatake ,  Shuichi Kubouchi ,  Kazuhiko Kajigaya

IPC分类号： G11C11/407 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4074 ,  G11C11/408 ,  G11C11/4087

摘要： In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.

摘要翻译： 在具有存储单元阵列的动态RAM中，其中动态存储单元布置在字线和一对位线中的一个位线之间的交叉点处，对应于电源电压的选择电平信号和对应于 低于电路接地电位的负电位被提供给字线。 通过由电路接地电位进行工作的读出放大器对一对位线读取的存储单元的信号和通过将电源电压降低等于地址选择MOSFET的阈值电压的量而形成的内部电压被放大。 动态RAM具有接收电源电压和电路接地电位的振荡器，以及接收由振荡器产生的振荡脉冲以产生负电位的电路。

公开(公告)号：US06198128B1

公开(公告)日：2001-03-06

申请号：US09390662

申请日：1999-09-07

申请人： Hisao Asakura ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Ryo Nagai ,  Masafumi Miyamoto ,  Masayuki Nakamura ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Masahiro Hyoma

发明人： Hisao Asakura ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Ryo Nagai ,  Masafumi Miyamoto ,  Masayuki Nakamura ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Masahiro Hyoma

IPC分类号： H01L2972

CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L21/823814

摘要： In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.

摘要翻译： 在用于抑制MISFET的短沟道效应的杂质与其主表面倾斜地引入半导体衬底的情况下，彼此相邻的栅电极被布置成使得沿与栅电极交叉的方向引入的杂质不会 被引入位于栅电极之间的半导体衬底的部分中，并且MISFET的源极区域被布置在栅电极之间的部分中。

公开(公告)号：US06178108B1

公开(公告)日：2001-01-23

申请号：US09258462

申请日：1999-02-26

申请人： Shinichi Miyatake ,  Shigekazu Kase ,  Masayuki Nakamura ,  Masatoshi Hasegawa ,  Kazuhiko Kajigaya

发明人： Shinichi Miyatake ,  Shigekazu Kase ,  Masayuki Nakamura ,  Masatoshi Hasegawa ,  Kazuhiko Kajigaya

IPC分类号： G11C1124

CPC分类号： G11C11/22

摘要： In a semiconductor memory device having a plurality of memory cells in which each memory cell is formed of an address selection MOSFET and an information storing capacitor and the plate voltage consisting of an intermediate potential is supplied to the common electrode of the information storing capacitor, the memory access is enabled by detecting indirect that the plate voltage has reached the predetermined potential near the intermediate potential with the voltage detecting circuit or timer circuit, inhibiting the selecting operation of the word lines or precharging the pair bit lines to the intermediate potential when the plate voltage is lower than the predetermined potential, and then canceling the above inhibit condition after the plate voltage has reached the predetermined potential.

摘要翻译： 在具有多个存储单元的半导体存储器件中，其中每个存储单元由地址选择MOSFET和信息存储电容器形成，并且由中间电位构成的板电压被提供给信息存储电容器的公共电极， 通过检测间接使用电压检测电路或定时器电路使板电压达到中间电位附近的预定电位来启用存储器访问，当板的电压被抑制时，字线的选择操作或预先充电到中间电位 电压低于预定电位，然后在板电压达到预定电位后取消上述禁止条件。

公开(公告)号：US5963467A

公开(公告)日：1999-10-05

申请号：US982457

申请日：1997-12-02

申请人： Shinichi Miyatake ,  Shigekazu Kase ,  Masayuki Nakamura ,  Masatoshi Hasegawa ,  Kazuhiko Kajigaya

发明人： Shinichi Miyatake ,  Shigekazu Kase ,  Masayuki Nakamura ,  Masatoshi Hasegawa ,  Kazuhiko Kajigaya

IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C11/407 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  G11C11/24

CPC分类号： G11C11/22

摘要： In a semiconductor memory device having a plurality of memory cells in which each memory cell is formed of an address selection MOSFET and an information storing capacitor and the plate voltage consisting of an intermediate potential is supplied to the common electrode of the information storing capacitor, the memory access is enabled by indirectly detecting that the plate voltage has reached a predetermined potential near a intermediate potential with the voltage detecting circuit or timer circuit, inhibiting the selecting operation of the word lines or precharging of the pair of bit lines to the intermediate potential when the plate voltage is lower than the predetermined potential, and then canceling the above inhibit condition after the plate voltage has reached the predetermined potential.

摘要翻译： 在具有多个存储单元的半导体存储器件中，其中每个存储单元由地址选择MOSFET和信息存储电容器形成，并且由中间电位构成的板电压被提供给信息存储电容器的公共电极， 通过用电压检测电路或定时器电路间接地检测到板电压已经达到中间电位附近的预定电位，使得能够进行存储器访问，从而阻止字线的选择操作或将一对位线预充电到中间电位 板电压低于预定电位，然后在板电压达到预定电位之后取消上述禁止条件。