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38 条记录 (耗时 0.018 秒)

    Method of shielding through silicon vias in a passive interposer
    2.
    发明授权
    Method of shielding through silicon vias in a passive interposer 有权
    在无源中介层中通过硅通孔屏蔽的方法

    公开(公告)号：US08618640B2

    公开(公告)日：2013-12-31

    申请号：US13194033

    申请日：2011-07-29

    申请人： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Meng-Lin Chung

    发明人： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Meng-Lin Chung

    IPC分类号： H01L23/552

    CPC分类号： H01L21/265 ,  H01L21/76802 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5225 ,  H01L23/552 ,  H01L2224/16

    摘要： A passive interposer apparatus with a shielded through silicon via (TSV) configuration is disclosed. The apparatus includes a p-doped substrate, wherein at least an upper portion of the p-doped substrate is heavily p-doped. An interlayer dielectric layer (ILD) is disposed over the upper portion of the p-doped substrate. A plurality of through silicon vias (TSVs) are formed through the ILD and the p-doped substrate. A plurality of shielding lines disposed between the TSVs electrically couple respective second metal contact pads to the upper portion of the p-doped substrate.

    摘要翻译： 公开了一种具有屏蔽硅通孔（TSV）配置的无源中介器。 该装置包括p掺杂衬底，其中至少p掺杂衬底的上部是高度p掺杂的。 层间电介质层（ILD）设置在p掺杂衬底的上部上。 通过ILD和p掺杂衬底形成多个穿通硅通孔（TSV）。 设置在TSV之间的多个屏蔽线将各个第二金属接触焊盘电耦合到p掺杂衬底的上部。

    Interposer Testing Using Dummy Connections
    3.
    发明申请
    Interposer Testing Using Dummy Connections 有权
    插入式测试使用虚拟连接

    公开(公告)号：US20120298410A1

    公开(公告)日：2012-11-29

    申请号：US13118129

    申请日：2011-05-27

    申请人： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Wei-Sho Hung

    发明人： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Wei-Sho Hung

    IPC分类号： H05K1/11 ,  H05K3/34

    CPC分类号： H01L23/49827 ,  H01L22/32 ,  H01L23/49822 ,  H01L2224/13025 ,  H01L2224/16

    摘要： An interconnection component includes a substrate, and an active through-substrate via (TSV) penetrating through the substrate. Active metal connections are formed over the substrate and electrically connected to the active TSV. At least one of a dummy pad and a dummy solder bump are formed at surfaces of the interconnection component. The dummy pad is over the substrate and electrically connected to the active TSV and the active metal connections. The dummy solder bump is under the substrate and electrically connected to the active metal connections. The dummy pad and the dummy solder bump are open ended.

    摘要翻译： 互连部件包括基板和穿透基板的有源贯穿基板通孔（TSV）。 有源金属连接形成在基板上并电连接到有源TSV。 在互连部件的表面形成虚拟焊盘和虚拟焊料凸点中的至少一个。 虚拟焊盘在基板上，并电连接到有源TSV和有源金属连接。 虚拟焊料凸块位于基板之下并电连接到有源金属连接。 虚拟焊盘和虚拟焊料凸块是开放式的。

    System and method of UV programming of non-volatile semiconductor memory
    4.
    发明授权
    System and method of UV programming of non-volatile semiconductor memory 有权
    非易失性半导体存储器的UV编程系统和方法

    公开(公告)号：US09190148B2

    公开(公告)日：2015-11-17

    申请号：US13425451

    申请日：2012-03-21

    申请人： Hsiang-Tai Lu ,  Chih-Hsien Lin

    发明人： Hsiang-Tai Lu ,  Chih-Hsien Lin

    IPC分类号： H01L29/788 ,  G11C16/02 ,  G11C16/04 ,  G11C16/22 ,  H01L27/115

    CPC分类号： H01L27/11521 ,  G11C16/02 ,  G11C16/0416 ,  G11C16/225 ,  G11C29/04 ,  G11C2029/0403 ,  H01L21/28273 ,  H01L21/3205 ,  H01L22/14 ,  H01L27/11558

    摘要： A semiconductor memory storage device includes first and second doped regions of a first type disposed in a semiconductor substrate. The first and second doped regions of the first type being laterally spaced from one another. A gate dielectric extends over the semiconductor substrate between the first and second doped regions, and a floating gate is disposed on the gate dielectric. An ultraviolet (UV) light blocking material is vertically disposed above the floating gate and has a size that covers the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light.

    摘要翻译： 半导体存储器存储器件包括设置在半导体衬底中的第一类型的第一和第二掺杂区域。 第一类型的第一和第二掺杂区域彼此横向间隔开。 栅极电介质在第一和第二掺杂区域之间的半导体衬底上延伸，并且浮置栅极设置在栅极电介质上。 紫外（UV）遮光材料垂直地设置在浮动栅极上方，并且具有覆盖浮动栅极的尺寸，使得在半导体存储器存储装置暴露于紫外光之后浮置栅极保持充电。

    Interposer testing using dummy connections
    5.
    发明授权
    Interposer testing using dummy connections 有权
    内插器测试使用虚拟连接

    公开(公告)号：US08664540B2

    公开(公告)日：2014-03-04

    申请号：US13118129

    申请日：2011-05-27

    申请人： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Wei-Sho Hung

    发明人： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Wei-Sho Hung

    IPC分类号： H05K1/11

    CPC分类号： H01L23/49827 ,  H01L22/32 ,  H01L23/49822 ,  H01L2224/13025 ,  H01L2224/16

    摘要： An interconnection component includes a substrate, and an active through-substrate via (TSV) penetrating through the substrate. Active metal connections are formed over the substrate and electrically connected to the active TSV. At least one of a dummy pad and a dummy solder bump are formed at surfaces of the interconnection component. The dummy pad is over the substrate and electrically connected to the active TSV and the active metal connections. The dummy solder bump is under the substrate and electrically connected to the active metal connections. The dummy pad and the dummy solder bump are open ended.

    摘要翻译： 互连部件包括基板和穿透基板的有源贯穿基板通孔（TSV）。 有源金属连接形成在基板上并电连接到有源TSV。 在互连部件的表面形成虚拟焊盘和虚拟焊料凸点中的至少一个。 虚拟焊盘在基板上，并电连接到有源TSV和有源金属连接。 虚拟焊料凸块位于基板之下并电连接到有源金属连接。 虚拟焊盘和虚拟焊料凸块是开放式的。

    Delay-locked loop
    6.
    发明授权
    Delay-locked loop 有权
    延迟锁定环路

    公开(公告)号：US08368445B2

    公开(公告)日：2013-02-05

    申请号：US13174798

    申请日：2011-07-01

    申请人： Chih-Hsien Lin ,  Chih-Wei Mu ,  Ming-Shih Yu

    发明人： Chih-Hsien Lin ,  Chih-Wei Mu ,  Ming-Shih Yu

    IPC分类号： H03L7/06

    CPC分类号： H03L7/095 ,  H03L7/0816 ,  H03L7/087 ,  H03L7/1075

    摘要： A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value.

    摘要翻译： 提供接收参考时钟信号并输出​​输出时钟信号的延迟锁定环路（DLL）。 DLL包括相位检测器，延迟链，防伪锁（AFL）电路和环路滤波器。 相位检测器根据参考时钟信号和输出时钟信号之间的相位比较器输出第一比较信号。 延迟链通过延迟不同间隔的参考时钟信号来产生多个选通时钟信号和输出时钟信号。 AFL电路根据参考时钟信号和选通时钟信号之间的相位比较输出第二比较信号。 环路滤波器根据第一和第二比较信号控制输出时钟信号的延迟时间，以将输出时钟信号的延迟时间锁定在预设值。

    Fiber container and associated optical communication device
    9.
    发明授权
    Fiber container and associated optical communication device 失效
    光纤容器及相关光通讯装置

    公开(公告)号：US06873778B2

    公开(公告)日：2005-03-29

    申请号：US10291836

    申请日：2002-11-12

    申请人： Tsung-Yueh Tsai ,  Chin-Hsiang Wang ,  Yu-Ting Lee ,  Chih-Hsien Lin

    发明人： Tsung-Yueh Tsai ,  Chin-Hsiang Wang ,  Yu-Ting Lee ,  Chih-Hsien Lin

    IPC分类号： B65H18/08 ,  G02B6/00 ,  H01S3/067

    CPC分类号： H01S3/06704

    摘要： A fiber container receiving optical fibers has a body, a space defined in the body, a reel disposed inside the body, wherein a groove is defined around the periphery of the reel. The optical fibers are twisted around the reel and received in the groove. Furthermore, the fiber container is able to apply to the active/passive optical communication device, such as an erbium doped fiber amplifier (EDFA) or a dense wavelength division multiplexer (DWDM).

    摘要翻译： 容纳光纤的纤维容器具有主体，在主体中限定的空间，设置在主体内部的卷轴，其中围绕卷轴的周边限定有凹槽。 光纤绕卷轴扭转并被接收在槽中。 此外，光纤容器能够应用于有源/无源光通信设备，例如掺铒光纤放大器（EDFA）或密集波分复用器（DWDM）。

    Method of forming resistors
    10.
    发明授权
    Method of forming resistors 有权
    形成电阻的方法

    公开(公告)号：US06732422B1

    公开(公告)日：2004-05-11

    申请号：US10037811

    申请日：2002-01-04

    申请人： Kong-Beng Thei ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

    发明人： Kong-Beng Thei ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

    IPC分类号： H01C1700

    CPC分类号： H01L28/20 ,  H01C7/006 ,  H01C17/0656 ,  H01C17/075 ,  H01L27/0802 ,  Y10T29/49082 ,  Y10T29/49087 ,  Y10T29/49098

    摘要： A method of forming a resistor is described which achieves improved resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilicon. The resistor has a rectangular first, second, third, fourth, and fifth resistor elements. A layer of protective dielectric is formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed. The conducting material in the exposed fourth and fifth resistor elements is then changed to a silicide to form low resistance contacts between the second and fourth resistor elements and between the second and fourth resistor elements. The second and third resistor elements are wider than the first resistor element and provide a low resistance contacts to the first resistor element. This provides a low voltage coefficient of resistance and thermal process stability for the resistor.

    摘要翻译： 描述形成电阻器的方法，其实现了电阻器稳定性和电阻的电压系数的改善。 电阻器由诸如掺杂硅或多晶硅的导电材料形成。 电阻器具有矩形的第一，第二，第三，第四和第五电阻元件。 在第一，第二和第三电阻器元件上形成保护电介质层，留下第四和第五电阻元件。 然后将暴露的第四和第五电阻器元件中的导电材料改变为硅化物以在第二和第四电阻器元件之间以及第二和第四电阻器元件之间形成低电阻触点。 第二和第三电阻器元件比第一电阻器元件宽，并且向第一电阻器元件提供低电阻触点。 这为电阻器提供了低电阻系数和热处理稳定性。