公开(公告)号：US11270778B2

公开(公告)日：2022-03-08

申请号：US16852162

申请日：2020-04-17

Applicant: Intel Corporation

Inventor： Han Zhao ,  Pranav Kalavade ,  Krishna K. Parat

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04

Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

公开(公告)号：US10903219B2

公开(公告)日：2021-01-26

申请号：US16412373

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Haitao Liu ,  Guangyu Huang ,  Krishna K. Parat ,  Shrotri B. Kunal ,  Srikant Jayanti

IPC: H01L29/76 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/51 ,  G11C11/56

Abstract: Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.

公开(公告)号：US10699790B2

公开(公告)日：2020-06-30

申请号：US16412269

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Krishna K. Parat ,  Pranav Kalavade ,  Koichi Kawai ,  Akira Goda

IPC: G11C16/04 ,  G11C16/16 ,  G11C8/12 ,  G11C16/34

Abstract: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.

公开(公告)号：US10658053B2

公开(公告)日：2020-05-19

申请号：US15715980

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Neal R. Mielke ,  Krishna K. Parat ,  Shyam Sunder Raghunathan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

公开(公告)号：US10325665B2

公开(公告)日：2019-06-18

申请号：US15836124

申请日：2017-12-08

Applicant: INTEL CORPORATION

Inventor： Richard Fastow ,  Xin Sun ,  Uday Chandrasekhar ,  Krishna K. Parat ,  Camila Jaramillo ,  Purval S. Sule ,  Aliasgar S. Madraswala

IPC: G11C5/14 ,  G11C16/28 ,  G11C16/16 ,  G11C16/34 ,  G11C11/4074 ,  G11C16/04

Abstract: A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.

公开(公告)号：US10290356B2

公开(公告)日：2019-05-14

申请号：US15050871

申请日：2016-02-23

Applicant: Intel Corporation

Inventor： Krishna K. Parat ,  Pranav Kalavade ,  Koichi Kawai ,  Akira Goda

IPC: G11C16/04 ,  G11C16/16 ,  G11C8/12 ,  G11C16/34

Abstract: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.

公开(公告)号：US20160372207A1

公开(公告)日：2016-12-22

申请号：US15183582

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Neal R. Mielke ,  Krishna K. Parat ,  Shyam Sunder Raghunathan

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

公开(公告)号：US09281318B2

公开(公告)日：2016-03-08

申请号：US14813398

申请日：2015-07-30

Applicant: Intel Corporation

Inventor： Haitao Liu ,  Chandra V. Mouli ,  Krishna K. Parat ,  Jie Sun ,  Guangyu Huang

IPC: H01L29/76 ,  H01L27/115 ,  H01L29/16 ,  H01L29/04 ,  G11C16/06

CPC classification number: H01L27/11582 ,  G11C16/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.

公开(公告)号：US10825831B1

公开(公告)日：2020-11-03

申请号：US16457694

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Randy J. Koval ,  Henok T. Mebrahtu ,  Krishna K. Parat

IPC: H01L27/115 ,  H01L29/40 ,  H01L21/02 ,  H01L21/32 ,  H01L27/11582 ,  H01L29/423 ,  H01L27/11556 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28

Abstract: Storage node configurations are described. A storage node (e.g., a floating gate or a charge trap layer of a three-dimensional (3D) NAND flash device) include a channel-facing surface with a radius of curvature. For example, a channel-facing surface of the storage node may be concave. A control gate-facing surface of the storage node may instead, or additionally, also include a radius of curvature. The radius of curvature of the channel-facing and/or control gate-facing surfaces of the storage node is less than or equal to the radius of the channel layer.

公开(公告)号：US10290642B2

公开(公告)日：2019-05-14

申请号：US15721771

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Haitao Liu ,  Guangyu Huang ,  Krishna K. Parat ,  Shrotri B. Kunal ,  Srikant Jayanti

IPC: H01L27/115 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L29/51 ,  H01L27/11582 ,  G11C11/56

Abstract: Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.