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1.发明申请公开(公告)号：US20250103075A1
公开(公告)日：2025-03-27
申请号：US18474156
申请日：2023-09-25
Applicant: Intel Corporation
Inventor： Khondker Ahmed , Nicolas Butzen , Nachiket Desai , Su Hwan Kim , Harish K. Krishnamurthy , Krishnan Ravichandran , Kaladhar Radhakrishnan , Jonathan Douglas
IPC: G05F1/56
Abstract: Embodiments herein relate to a stacked semiconductor structure which includes a first voltage regulator (VR), external to a package, for supplying current to a compute die in the package. When the required current exceeds a threshold, an additional current source is activated. The additional current source can include a second VR, also external to the package, for supplying current to an integrated voltage regulator (IVR) in the package. The IVR performs voltage down conversion and current multiplication to output a portion of the required current above the threshold, while the output of the first VR is capped at the threshold.
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公开(公告)号：US20210271277A1
公开(公告)日：2021-09-02
申请号：US17253096
申请日：2019-09-06
Applicant: Intel Corporation
Inventor： Khondker Ahmed , Harish Krishnamurthy , Krishnan Ravichandran
Abstract: A Computational Digital Low Dropout (CDLDO) regulator is described that computes a required solution for regulating an output supply as opposed to traditional feedback controllers. The CDLDO regulator is Moore's Law friendly in that it can scale with technology nodes. For example, CDLDO regulator of some embodiments uses a digital approach to voltage regulation, which is orders of magnitude faster than traditional digital LDOs and enables regulation at GHz speeds, making fast dynamic DVFS a reality. The CDLDO also autonomously tunes out the effects of process-voltage-temperature (PVT) and other non-idealities making the settling time totally variation tolerant.
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3.发明申请公开(公告)号：US20210103308A1
公开(公告)日：2021-04-08
申请号：US17100603
申请日：2020-11-20
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Harish Krishnamurthy , Krishnan Ravichandran , Vivek De , Scott Chiu , Claudia Patricia Barrera Gonzalez , Jing Han , Rajasekhara Madhusudan Narayana Bhatla
Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.
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4.发明授权公开(公告)号：US10958079B2
公开(公告)日：2021-03-23
申请号：US15939120
申请日：2018-03-28
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Khondker Z. Ahmed , Vivek K. De , Nachiket V. Desai , Suhwan Kim , Harish K. Krishnamurthy , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav A. Vaidya , Sriram R. Vangal
Abstract: In one embodiment, an energy harvesting system includes multiple-input-multiple-output switched-capacitor (MIMOSC) circuitry comprising a plurality of switched-capacitor circuit units to receive a plurality of direct current (DC) input voltages at respective input terminals of the switched-capacitor circuit unit, combine the received DC input voltages, and provide the combined DC input voltages at an output terminal of the switched-capacitor circuit unit. The energy harvesting system also includes maximum power point tracking (MPPT) circuitry coupled to switches of the switched-capacitor circuit units of the MIMOSC circuitry. The MPPT circuitry is to provide a plurality of switching signals to the switches of the switched-capacitor circuit units. The MIMOSC circuitry is to provide a plurality of DC output voltages to respective loads based on the switching signals from the MPPT circuitry.
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公开(公告)号：US10298117B2
公开(公告)日：2019-05-21
申请号：US15638643
申请日：2017-06-30
Applicant: INTEL CORPORATION
Inventor： Harish Krishnamurthy , Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
Abstract: Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.
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Patent Agency Ranking
公开(公告)号：US20180375433A1
公开(公告)日：2018-12-27
申请号：US15632086
申请日：2017-06-23
Applicant: INTEL CORPORATION
Inventor： Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Harish Krishnamurthy , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
CPC classification number: H02M3/1582 , G05F1/67 , H02M1/08 , H02M2001/0003 , H02M2001/0009 , H02M2001/0025
Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.
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7.发明授权公开(公告)号：US09490701B2
公开(公告)日：2016-11-08
申请号：US14325310
申请日：2014-07-07
Applicant: Intel Corporation
Inventor： George E. Matthew , Jessica Gullbrand , Krishnan Ravichandran , Willem M. Beltman , Karthik Sankaranarayanan , Sheldon Weng , Wayne L. Proefrock , Harish K. Krishnamurthy , Pavan Kumar
CPC classification number: H02M3/158 , H02M1/44 , H02M3/005 , H02M3/157 , H02M3/1582 , H02M2003/1566
Abstract: Methods and apparatus relating to reducing switching noise and improving transient response in voltage regulators are described. In an embodiment, one or more pulses are inserted into an output waveform of a voltage regulator. The one or more pulses introduce multiple frequencies into the output waveform of the voltage regulator (e.g., to reduce acoustic noise). In another embodiment, the output voltage of a voltage regulator is modified in response to comparison of the output voltage with at least one of a plurality of threshold values. The plurality of threshold values includes an upper trigger point voltage value and a lower trigger point voltage value. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了降低开关噪声和改善稳压器瞬态响应的方法和装置。 在一个实施例中，一个或多个脉冲被插入到电压调节器的输出波形中。 一个或多个脉冲将多个频率引入电压调节器的输出波形（例如，以减少声学噪声）。 在另一个实施例中，响应于输出电压与多个阈值中的至少一个的比较来修改电压调节器的输出电压。 多个阈值包括上触发点电压值和下触发点电压值。 还公开并要求保护其他实施例。
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公开(公告)号：US11675379B2
公开(公告)日：2023-06-13
申请号：US17253096
申请日：2019-09-06
Applicant: Intel Corporation
Inventor： Khondker Ahmed , Harish Krishnamurthy , Krishnan Ravichandran
Abstract: A Computational Digital Low Dropout (CDLDO) regulator is described that computes a required solution for regulating an output supply as opposed to traditional feedback controllers. The CDLDO regulator is Moore's Law friendly in that it can scale with technology nodes. For example, CDLDO regulator of some embodiments uses a digital approach to voltage regulation, which is orders of magnitude faster than traditional digital LDOs and enables regulation at GHz speeds, making fast dynamic DVFS a reality. The CDLDO also autonomously tunes out the effects of process-voltage-temperature (PVT) and other non-idealities making the settling time totally variation tolerant.
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公开(公告)号：US10108212B2
公开(公告)日：2018-10-23
申请号：US14861997
申请日：2015-09-22
Applicant: Intel Corporation
Inventor： Sunghyun Park , Stephen Kim , Krishnan Ravichandran , Sriram R. Vangal , Vivek K. De
Abstract: Some embodiments include apparatuses and methods having a power switching unit to receive a first voltage and provide a second voltage having a value based on a value of the first voltage, a first loop to provide digital control information to control a switching of the power switching unit in order to maintain a relationship between the value of the second voltage and a value of a reference voltage, and a second loop coupled to the power switching unit and the first loop to calculate a value of energy consumption of at least a portion of the apparatus based at least on the digital control information.
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公开(公告)号：US10069397B2
公开(公告)日：2018-09-04
申请号：US14757802
申请日：2015-12-23
Applicant: Intel Corporation
Inventor： Vaibhav Vaidya , Pavan Kumar , Krishnan Ravichandran , Vivek K. De
Abstract: Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry. The switch controller circuitry includes dead time logic circuitry to determine an estimated dead time interval between a turn off of a first switch and a turn on of a second switch. The first switch and the second switch are coupled at a switched node. The estimated dead time interval is determined based, at least in part, on a difference between an input voltage, Vin, and a switched voltage, Vsw, detected at the switched node just prior to turning off the first switch, a parasitic capacitance, Cpar, associated with the switched node and a maximum inductor current, IL,max. The difference between Vin and Vsw represents the maximum inductor current.
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