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    Fast boot up memory controller
    2.
    发明授权
    Fast boot up memory controller 有权

    公开(公告)号：US10552643B2

    公开(公告)日：2020-02-04

    申请号：US15392912

    申请日：2016-12-28

    Applicant: INTEL CORPORATION

    Inventor： John V. Lovelace ,  Sreenivas Mandava ,  Debaleena Das

    IPC: G06F21/79

    Abstract: A method performed by a memory controller is described. The method includes, during boot up, issuing a command to a memory to cause the memory to zero out its content. The method also includes bypassing a descrambler when reading from a location in the memory that has not had its zeroed out content written over the scrambled data. The method also includes processing read data with the descrambler when reading from a location in the memory that has had its zeroed out content written over with scrambled data.

    Temperature-based runtime variability in victim address selection for probabilistic schemes for row hammer
    3.
    发明授权
    Temperature-based runtime variability in victim address selection for probabilistic schemes for row hammer 有权

    公开(公告)号：US12099388B2

    公开(公告)日：2024-09-24

    申请号：US17130686

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Sreenivas Mandava ,  Anders Fogh

    IPC: G06F1/20 ,  G06F12/02 ,  G06F13/16

    CPC classification number: G06F1/206 ,  G06F12/023 ,  G06F13/1668 ,  G06F2212/1032

    Abstract: A probabilistic scheme that uses temperature to reload an LFSR at runtime introduces randomness to prevent row hammer attacks. In one example, a memory controller includes input/output (I/O) interface circuitry to receive memory access requests from a processor. A linear feedback shift register (LFSR) in the memory controller is shifted in response to receipt of a memory access request to a target address. The shift register is compared a value in the LFSR with a pre-determined value. If the value in the LFSR is equal to the predetermined value, a refresh is triggered to one or more neighboring addresses of the target address. The LFSR is reloaded with one of multiple seeds based on a temperature (for example, from an on-die thermal sensor, a DIMM sensor, and/or other temperature). Selecting one of multiple seeds based on temperature on the fly makes the scheme unpredictable and robust against row hammer.

    Techniques for probabilistic dynamic random access memory row repair
    7.
    发明授权
    Techniques for probabilistic dynamic random access memory row repair 有权

    公开(公告)号：US10102886B2

    公开(公告)日：2018-10-16

    申请号：US15269657

    申请日：2016-09-19

    Applicant: Intel Corporation

    Inventor： John H. Crawford ,  Brian S. Morris ,  Sreenivas Mandava ,  Raj K. Ramanujan

    IPC: G11C7/02 ,  G06F13/16 ,  G11C11/406

    Abstract: Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.

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