公开(公告)号：US20240045830A1

公开(公告)日：2024-02-08

申请号：US18450685

申请日：2023-08-16

Applicant: Intel Corporation

Inventor： Joydeep RAY ,  Aravindh ANANTARAMAN ,  Abhishek R. APPU ,  Altug KOKER ,  Elmoustapha OULD-AHMED-VALL ,  Valentin ANDREI ,  Subramaniam MAIYURAN ,  Nicolas GALOPPO VON BORRIES ,  Varghese GEORGE ,  Mike MACPHERSON ,  Ben ASHBAUGH ,  Murali RAMADOSS ,  Vikranth VEMULAPALLI ,  William SADLER ,  Jonathan PEARCE ,  Sungye KIM

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

CPC classification number: G06F15/8069 ,  G06F9/30163 ,  G06F9/3877 ,  G06T15/005 ,  G06F9/3836

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220261949A1

公开(公告)日：2022-08-18

申请号：US17734983

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Chandra S. GURRAM ,  Gang Y. CHEN ,  Subramaniam MAIYURAN ,  Supratim PAL ,  Ashutosh GARG ,  Jorge E. PARRA ,  Darin M. STARKEY ,  Guei-Yuan LUEH ,  Wei-Yu CHEN

IPC: G06T1/20 ,  G06T1/60

Abstract: Examples described herein relate to a software and hardware optimization that manages scenarios where a write operation to a register is less than an entirety of the register. A compiler detects instructions that make partial writes to the same register, groups such instructions, and provides hints to hardware of the partial write. The execution unit combines the output data for grouped instructions and updates the destination register as single write instead of multiple separate partial writes.

公开(公告)号：US20240061700A1

公开(公告)日：2024-02-22

申请号：US18239489

申请日：2023-08-29

Applicant: INTEL CORPORATION

Inventor： Rajesh SANKARAN ,  Bret TOLL ,  William RASH ,  Subramaniam MAIYURAN ,  Gang CHEN ,  Varghese GEORGE

IPC: G06F9/455 ,  G06F12/1009 ,  G06T1/20

CPC classification number: G06F9/45558 ,  G06F12/1009 ,  G06T1/20 ,  G06F2009/4557 ,  G06F2009/45583 ,  G06F2009/45591

Abstract: Graphics processing systems and methods are described. A graphics processing apparatus may comprise one or more graphics processing engines, a memory, a memory management unit (MMU) including a GPU second level page table and GPU dirty bit tracking, and a provisioning agent to receive a request from a virtual machine monitor (VMM) to provision a subcluster of graphics processing apparatuses, the subcluster including a plurality of graphics processing engines from a plurality of graphics processing apparatuses connected using a scale-up fabric, provision the scale-up fabric to route data within the subcluster of graphics processing apparatuses, and provision a plurality of resources on the graphics processing apparatus for the subcluster based on the request from the VMM.

公开(公告)号：US20210149680A1

公开(公告)日：2021-05-20

申请号：US17095585

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Prasoonkumar SURTI ,  Guei-Yuan LUEH ,  Adam T. LAKE ,  Jill BOYCE ,  Subramaniam MAIYURAN ,  Lidong XU ,  James M. HOLLAND ,  Vasanth RANGANATHAN ,  Nikos KABURLASOS ,  Altug KOKER ,  Abhishek R. APPU

IPC: G06F9/38 ,  G06F12/084 ,  G06F9/54 ,  G06F9/50 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US20210089316A1

公开(公告)日：2021-03-25

申请号：US16582433

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： William RASH ,  Subramaniam MAIYURAN ,  Varghese GEORGE ,  Bret L. TOLL ,  Rajesh SANKARAN ,  Robert S. CHAPPELL ,  Supratim PAL ,  Alexander F. HEINECKE ,  Elmoustapha OULD-AHMED-VALL ,  Gang CHEN

IPC: G06F9/38 ,  G06N3/04 ,  G06N3/08 ,  G06F15/80

Abstract: Disclosed embodiments relate to deep learning implementations using systolic arrays and fused operations. In one example, a processor includes fetch and decode circuitry to fetch and decode an instruction having fields to specify an opcode and locations of a destination and N source matrices, the opcode indicating the processor is to load the N source matrices from memory, perform N convolutions on the N source matrices to generate N feature maps, and store results of the N convolutions in registers to be passed to an activation layer, wherein the processor is to perform the N convolutions and the activation layer with at most one memory load of each of the N source matrices. The processor further includes scheduling circuitry to schedule execution of the instruction and execution circuitry to execute the instruction as per the opcode.

公开(公告)号：US20250068588A1

公开(公告)日：2025-02-27

申请号：US18822815

申请日：2024-09-03

Applicant: Intel Corporation

Inventor： Joydeep RAY ,  Aravindh ANANTARAMAN ,  Abhishek R. APPU ,  Altug KOKER ,  Elmoustapha OULD-AHMED-VALL ,  Valentin ANDREI ,  Subramaniam MAIYURAN ,  Nicolas GALOPPO VON BORRIES ,  Varghese GEORGE ,  Mike MACPHERSON ,  Ben ASHBAUGH ,  Murali RAMADOSS ,  Vikranth VEMULAPALLI ,  William SADLER ,  Jonathan PEARCE ,  Sungye KIM

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240184739A1

公开(公告)日：2024-06-06

申请号：US18432859

申请日：2024-02-05

Applicant: INTEL CORPORATION

Inventor： Joydeep RAY ,  Niranjan COORAY ,  Subramaniam MAIYURAN ,  Altug KOKER ,  Prasoonkumar SURTI ,  Varghese GEORGE ,  Valentin ANDREI ,  Abhishek APPU ,  Guadalupe GARCIA ,  Pattabhiraman K ,  Sungye KIM ,  Sanjay KUMAR ,  Pratik MAROLIA ,  Elmoustapha OULD-AHMED-VALL ,  Vasanth RANGANATHAN ,  William SADLER ,  Lakshminarayanan STRIRAMASSARMA

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

公开(公告)号：US20230418617A1

公开(公告)日：2023-12-28

申请号：US18339454

申请日：2023-06-22

Applicant: INTEL CORPORATION

Inventor： Christopher J. HUGHES ,  Prasoonkumar SURTI ,  Guei-Yuan LUEH ,  Adam T. LAKE ,  Jill BOYCE ,  Subramaniam MAIYURAN ,  Lidong XU ,  James M. HOLLAND ,  Vasanth RANGANATHAN ,  Nikos KABURLASOS ,  Altug KOKER ,  Abhishek R. Appu

IPC: G06F9/38 ,  G06F12/084 ,  G06T1/60 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F9/3891 ,  G06F12/084 ,  G06T1/60 ,  G06F9/5066 ,  G06F9/544

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US20220066737A1

公开(公告)日：2022-03-03

申请号：US17003334

申请日：2020-08-26

Applicant: Intel Corporation

Inventor： Shuai MU ,  Cristina S. ANDERSON ,  Subramaniam MAIYURAN

IPC: G06F7/548 ,  G06F7/44 ,  G06F17/17 ,  G06F9/30 ,  G06F9/38 ,  G06F9/54

Abstract: Examples described herein relate to instructions to request performance of tanh and sigmoid instructions. For example, a compiler can generate native tanh instructions to perform tanh. In some examples, a tanh function can be compiled into instructions that include an instruction to perform either tanh(input) or tanh(input)/input depending on a value of the input to generate an intermediate output; an instruction to cause a performance of generation of scale factor based on the input; and an instruction to cause performance of a multiplication operation on the intermediate result with the scale factor. For example, a sigmoid function can be compiled to cause a math pipeline to perform a range check and performs operations based on a range.

公开(公告)号：US20240004713A1

公开(公告)日：2024-01-04

申请号：US18363339

申请日：2023-08-01

Applicant: Intel Corporation

Inventor： Abhishek R. APPU ,  Altug KOKER ,  Balaji VEMBU ,  Joydeep RAY ,  Kamal SINHA ,  Prasoonkumar SURTI ,  Kiran C. VEERNAPU ,  Subramaniam MAIYURAN ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06F1/329 ,  G06F9/48 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06F9/5016 ,  G06F9/5044 ,  G06F1/329 ,  G06F9/4893 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  Y02D10/00 ,  G06T2200/28

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.