公开(公告)号：US20180323078A1

公开(公告)日：2018-11-08

申请号：US15774255

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Stephanie A. BOJARSKI ,  Manish CHANDHOK ,  Todd R. YOUNKIN ,  Eungnak HAN ,  Kranthi Kumar ELINENI ,  Ashish N. GAIKWAD ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Hui Jae YOO

IPC: H01L21/311 ,  H01L21/033

CPC classification number: H01L21/31144 ,  G03F7/0002 ,  H01L21/0337 ,  H01L21/0338

Abstract: A method including forming a target pattern of a target material on a surface of a substrate; depositing a block copolymer on the surface of the substrate, wherein one of two blocks of the block copolymer preferentially aligns to the target material and the two blocks self assemble after deposition into repeating lamellar bodies on the surface of the substrate; selectively retaining one of the two blocks of the block copolymer over the other as a polymer pattern; and patterning the substrate with the polymer pattern. An apparatus including an integrated circuit substrate including a plurality of contact points and a dielectric layer on the contact points; a target pattern formed in a surface of the dielectric layer; and a self-assembled layer of repeating alternating bodies of a block copolymer, wherein one of two blocks of the block copolymer is preferentially aligned to the target pattern.

公开(公告)号：US20170345643A1

公开(公告)日：2017-11-30

申请号：US15529482

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Todd R. YOUNKIN ,  Michael J. LEESON ,  James M. BLACKWELL ,  Ernisse S. PUTNA ,  Marie KRYSAK ,  Rami HOURANI ,  Eungnak HAN ,  Robert L. BRISTOL

IPC: H01L21/027 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/0271 ,  G03F7/0035 ,  G03F7/094 ,  G03F7/095 ,  G03F7/115 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/528 ,  H01L2224/16225

Abstract: Photodefinable alignment layers for chemical assisted patterning and approaches for forming photodefinable alignment layers for chemical assisted patterning are described. An embodiment of the invention may include disposing a chemically amplified resist (CAR) material over a hardmask that includes a switch component. The CAR material may then be exposed to form exposed resist portions. The exposure may produces acid in the exposed portions of the CAR material that interact with the switch component to form modified regions of the hardmask material below the exposed resist portions.

公开(公告)号：US20190189500A1

公开(公告)日：2019-06-20

申请号：US16284568

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Todd R. YOUNKIN ,  Eungnak HAN ,  Jasmeet S. CHAWLA ,  Marie KRYSAK ,  Hui Jae YOO ,  Tristan A. TRONIC

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

公开(公告)号：US20180323104A1

公开(公告)日：2018-11-08

申请号：US15772013

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Todd R. YOUNKIN ,  Eungnak HAN ,  Shane M. HARLSON ,  James M. BLACKWELL

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/027 ,  G03F7/00 ,  G03F7/004 ,  G03F7/16

CPC classification number: H01L21/76897 ,  G03F7/0002 ,  G03F7/0045 ,  G03F7/16 ,  H01L21/0274 ,  H01L21/76807 ,  H01L21/76816 ,  H01L23/48 ,  H01L23/532 ,  H01L23/5329 ,  H01L23/53295

Abstract: Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate. The method also includes forming a triblock copolymer layer above the lower metallization layer. The method also includes segregating the triblock copolymer layer to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer, where the third segregated block component is photosensitive. The method also includes irradiating and developing select locations of the third segregated block component to provide via openings over the metal lines of the lower metallization layer.

公开(公告)号：US20180204760A1

公开(公告)日：2018-07-19

申请号：US15744018

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Todd R. YOUNKIN ,  Eungnak HAN ,  Jasmeet S. (JZ) CHAWLA ,  Marie KRYSAK ,  Hui Jae YOO ,  Tristan A. TRONIC

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

公开(公告)号：US20170235228A1

公开(公告)日：2017-08-17

申请号：US15504469

申请日：2014-09-22

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Todd R. YOUNKIN ,  Sang H. LEE ,  Charles H. WALLACE

IPC: G03F7/20 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027

Abstract: Techniques related to multi-pass patterning lithography, device structures, and devices formed using such techniques are discussed. Such techniques include exposing a resist layer disposed over a grating pattern with non-reflecting radiation to generate an enhanced exposure portion within a trench of the grating pattern and developing the resist layer to form a pattern layer having a pattern structure within the trench of the grating pattern.