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1.发明申请公开(公告)号：US20190243577A1
公开(公告)日：2019-08-08
申请号：US16388761
申请日：2019-04-18
Applicant: INTEL CORPORATION
Inventor： David J. PELSTER , David B. CARLTON , Mark Anthony GOLEZ , Xin GUO , Aliasgar S. MADRASWALA , Sagar S. SIDHPURA , Sagar UPADHYAY , Neelesh VEMULA , Yogesh B. WAKCHAURE , Ye ZHANG
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.
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公开(公告)号：US20190227751A1
公开(公告)日：2019-07-25
申请号：US16370743
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Ali KHAKIFIROOZ , Pranav KALAVADE , Xin GUO , Aliasgar S. MADRASWALA , Bharat M. PATHAK
Abstract: A memory device is designed to store data in multilevel storage cells (MLC storage cells). The memory device includes a controller that dynamically writes data to the storage cells according to a first MLC density or a second MLC density. The second density is less dense than the first density. For example, the controller can determine to use the first density when there is sufficient write bandwidth to program the storage cells at the first density. When the write throughput increases, the controller can program the same MLC storage cells at the second density instead of the first density, using the same program process and voltage.
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公开(公告)号：US20190146669A1
公开(公告)日：2019-05-16
申请号：US16105363
申请日：2018-08-20
Applicant: INTEL CORPORATION
Inventor： Aliasgar S. MADRASWALA , Yogesh B. WAKCHAURE , David B. CARLTON , Xin GUO , Ryan J. NORTON
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0659 , G06F3/0679 , G06F3/0688
Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.
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4.发明申请公开(公告)号：US20200027503A1
公开(公告)日：2020-01-23
申请号：US16586214
申请日：2019-09-27
Applicant: Intel Corporation
Inventor： Lei CHEN , Yogesh B. WAKCHAURE , Aliasgar S. MADRASWALA , Xin GUO , Cole UHLMAN
Abstract: A method and apparatus to reduce read retry operations in a NAND Flash memory is provided. To reduce the number of read retries for future reads, a word line group is assigned an optimal read voltage, the reference voltage that results in eliminating the read error for the word line is selected as the optimal read voltage (also referred to as a “sticky voltage”) for the word line group to be used for a next read of the page. An optimal read voltage per word line group for the page per NAND Flash memory die is stored in the lookup table. Storing an optimal read voltage per word line group instead of per die reduces the number of read retries.
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公开(公告)号：US20180181323A1
公开(公告)日：2018-06-28
申请号：US15391760
申请日：2016-12-27
Applicant: INTEL CORPORATION
Inventor： Jing-Jing LI , Xin GUO , Brennan A. WATT , Ye ZHANG
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F1/30 , G06F3/0661 , G06F3/0679 , G06F11/1441 , G06F11/2015
Abstract: A first context of a non-volatile memory device is stored starting from a first location of a band of the non-volatile memory device, and an indication is made in a metadata that the first context has been stored starting from the first location of the band. A second context of the non-volatile memory device is stored starting from a second location of the band and an indication is made in the metadata that the second context has been stored starting from the second location of the band.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20170046073A1
公开(公告)日：2017-02-16
申请号：US14822793
申请日：2015-08-10
Applicant: INTEL CORPORATION
Inventor： Xin GUO , Feng ZHU , Eric L. HOFFMAN , Jing-Jing LI , David J. PELSTER
CPC classification number: G06F3/0608 , G06F3/064 , G06F3/0679 , G06F12/10 , G06F2212/1044 , G06F2212/152 , G06F2212/202 , G06F2212/253 , G06F2212/657 , G11C29/76
Abstract: Provided are a method and apparatus for remapping logical to physical addresses for a non-volatile memory having dies. Bands extend through the dies and planes in the dies extending through the bands define addressable blocks. A first remapping of a logical-to-physical mapping is performed by remapping logical addresses of blocks in a first end of the bands that map to defective physical blocks to map to good physical blocks at a second end of the bands. After performing the first remapping, a second remapping of the logical-to-physical mapping is performed by remapping logical addresses in the second end of bands that map to defective blocks to map to good physical blocks in the first end of bands.
Abstract translation: 提供了一种用于对具有管芯的非易失性存储器重新映射逻辑到物理地址的方法和装置。 带延伸穿过模具，延伸穿过带的模具中的平面定义可寻址块。 通过重新映射映射到不良物理块的频带的第一端中的块的逻辑地址，以在频带的第二端映射到良好的物理块来执行逻辑到物理映射的第一重映射。 在执行第一重映射之后，通过重新映射映射到缺陷块的频带的第二端中的逻辑地址来进行逻辑到物理映射的第二重映射，以映射到频带的第一端中的良好的物理块。
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公开(公告)号：US20190227749A1
公开(公告)日：2019-07-25
申请号：US16367638
申请日：2019-03-28
Applicant: Intel Corporation
Inventor： Yogesh B. WAKCHAURE , Aliasgar S. MADRASWALA , David J. PELSTER , Donia SEBASTIAN , Curtis GITTENS , Xin GUO , Neelesh VEMULA , Varsha REGULAPATI , Naga Kiranmayee UPADHYAYULA
Abstract: Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.
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8.发明申请公开(公告)号：US20190043593A1
公开(公告)日：2019-02-07
申请号：US15959538
申请日：2018-04-23
Applicant: Intel Corporation
Inventor： Xin GUO , Yu DU , Curtis GITTENS , David J. PELSTER , Donia SEBASTIAN
Abstract: A reduction in Quality of Service (QoS) latency for host read commands in a power limited operation mode in a storage device is provided. A priority level is assigned to a host command using weighted round robin arbitration. Power resources are allocated based on the priority levels assigned to host commands to minimize host read command latency in the power limited operation mode.
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公开(公告)号：US20190042356A1
公开(公告)日：2019-02-07
申请号：US16145983
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Lei CHEN , Xin GUO , Shu-Jen LEE , Chu-hsiang TENG , Scott NELSON , Donia SEBASTIAN
CPC classification number: G06F11/1012 , G11C16/26 , G11C16/3431 , G11C29/021 , G11C29/028 , G11C2029/0409 , G11C2029/0411
Abstract: Examples described herein can be used to reduce a number of re-read operations and potentially avoid data recovery operations, which can be time consuming. A determination can be made of a read voltage to apply during an operation to cause a read of data stored in a region of a memory device. The region of the memory device can be read using the read voltage. If the region is not successfully read, then an error level indication can be measured and a second read voltage can be determined for a re-read operation. If the re-read operation is not successful, then a second error level indication can be measured for the re-read operation. A third read voltage can be selected based on the change from the error level indication to the second error level indication.
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10.发明申请公开(公告)号：US20180040367A1
公开(公告)日：2018-02-08
申请号：US15228699
申请日：2016-08-04
Applicant: INTEL CORPORATION
Inventor： Wei WU , Yi ZOU , Jawad B. KHAN , Xin GUO
CPC classification number: G11C11/5628 , G06F3/0608 , G06F3/0661 , G06F3/0688 , G11C7/1006 , G11C11/5642 , G11C16/10 , G11C2211/5641 , G11C2211/5648
Abstract: Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage cells are organized into storage cell groups to which data is written. Each storage cell group is programmed to store a first number of bits of information. A memory controller selects a second number of bits of information from pages less than the first number of bits of information. The memory controller programs the storage cells of the storage cell group using threshold voltage levels from a second number of threshold voltage levels, wherein the second number of threshold voltage levels is less than the first number of threshold voltage levels and comprises a lowest of the first number of threshold voltage levels.
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