公开(公告)号：US20240105678A1

公开(公告)日：2024-03-28

申请号：US18243231

申请日：2023-09-07

Applicant: Infineon Technologies AG

Inventor： Thorsten MEYER ,  Angela KESSLER ,  Thorsten SCHARF

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/19 ,  H01L24/24 ,  H01L25/50 ,  H01L2224/19 ,  H01L2224/24137

Abstract: A chip package is provided. The chip package includes an electrically conductive carrier structure, a first power chip on the carrier structure having a control contact pad and a second power chip on the carrier structure having a control contact pad. The first and second power chips are arranged with their respective control contact pad facing a redistribution layer. A logic chip is arranged with a logic contact pad facing a redistribution layer, wherein the redistribution layer connects the logic contact pad with the respective control pads of the power chips.

公开(公告)号：US20170162476A1

公开(公告)日：2017-06-08

申请号：US15367920

申请日：2016-12-02

Applicant: Infineon Technologies AG

Inventor： Thorsten MEYER ,  Klaus Pressel ,  Maciej Wojnowski

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49541 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162

Abstract: An electronic device comprising a semiconductor package having a first main surface region and a second main surface region and comprising a semiconductor chip comprising at least one chip pad in the second main surface region and a connector block comprising at least one first electrically conductive through connection and at least one second electrically conductive through connection extending with different cross-sectional areas between the first main surface region and the second main surface region and being arranged side-by-side with the semiconductor chip.

公开(公告)号：US20230117806A1

公开(公告)日：2023-04-20

申请号：US17952688

申请日：2022-09-26

Applicant: Infineon Technologies AG

Inventor： Thorsten MEYER ,  Thomas BEHRENS ,  Christian IRRGANG ,  Frank ZUDOCK

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/16 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/29

Abstract: Semiconductor packages and methods for manufacturing are disclosed. In one example, a method for manufacturing a semiconductor package includes providing an electrically conductive chip carrier including a mounting surface and a protrusion extending out of the mounting surface. At least one semiconductor chip is arranged on the mounting surface. The method further includes encapsulating the protrusion and the at least one semiconductor chip in an encapsulation material, wherein surfaces of the protrusion and the at least one semiconductor chip facing away from the mounting surface remain uncovered by the encapsulation material. An electrical redistribution layer is formed over the surfaces of the protrusion and the at least one semiconductor chip facing away from the mounting surface. The electrical redistribution layer provides an electrical connection between the protrusion and the at least one semiconductor chip.

公开(公告)号：US20210167036A1

公开(公告)日：2021-06-03

申请号：US17101339

申请日：2020-11-23

Applicant: Infineon Technologies AG

Inventor： Oliver HELLMUND ,  Barbara EICHINGER ,  Thorsten MEYER ,  Ingo MURI

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/78

Abstract: A semiconductor device includes a semiconductor die, an electrical contact arranged on a surface of the semiconductor die, and a metal layer arranged on the electrical contact, wherein the metal layer includes a singulated part of at least one of a metal foil, a metal sheet, a metal leadframe, or a metal plate. When viewed in a direction perpendicular to the surface of the semiconductor die, a footprint of the electrical contact and a footprint of the metal layer are substantially congruent.

公开(公告)号：US20170317016A1

公开(公告)日：2017-11-02

申请号：US15497267

申请日：2017-04-26

Applicant: Infineon Technologies AG

Inventor： Alexander HEINRICH ,  Bernd GOLLER ,  Thorsten MEYER ,  Gerald OFNER

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip.

公开(公告)号：US20170178993A1

公开(公告)日：2017-06-22

申请号：US15382693

申请日：2016-12-18

Applicant: Infineon Technologies AG

Inventor： Thorsten MEYER ,  Edward Fuergut ,  Gerald Ofner ,  Petteri Palm

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3157 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/00 ,  H01L24/09 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81191 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An electronic component which comprises an electrically insulating layer having at least one through hole, a patterned electrically conductive structure at least partially on the electrically insulating layer, an electronic chip electrically coupled with the patterned electrically conductive structure, an encapsulant at least partially encapsulating the electronic chip, and at least one electrically conductive contact structure at least partially in the at least one through hole in contact with at least part of the patterned electrically conductive structure.

公开(公告)号：US20220165687A1

公开(公告)日：2022-05-26

申请号：US17502084

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Thorsten MEYER ,  Thomas BEMMERL ,  Martin GRUBER ,  Martin Richard NIESSNER

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48

Abstract: A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, an encapsulant encapsulating at least part of the electronic component and at least part of the carrier and having a bottom side at a first vertical level. At least one lead is electrically coupled with the electronic component and comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at the bottom side of the encapsulant. A functional structure at the bottom side extends up to a second vertical level different from the first vertical level.

公开(公告)号：US20220157774A1

公开(公告)日：2022-05-19

申请号：US17502163

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Thorsten MEYER ,  Martin GRUBER ,  Thorsten SCHARF

IPC: H01L23/00 ,  H01L21/56

Abstract: A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer.