公开(公告)号：US20250112164A1

公开(公告)日：2025-04-03

申请号：US18374932

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Onur OZKAN ,  Ryan CARRAZZONE ,  Rui ZHANG ,  Haobo CHEN ,  Ziyin LIN ,  Yiqun BAI ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Bin MU ,  Mohit GUPTA ,  Jeremy D. ECTON ,  Brandon C. MARIN ,  Xiaoying GUO ,  Steve S. CHO ,  Ali LEHAF ,  Venkata Rajesh SARANAM ,  Shripad GOKHALE ,  Kartik SRINIVASAN ,  Edvin CETEGEN ,  Mine KAYA ,  Nicholas S. HAEHN ,  Deniz TURAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.

公开(公告)号：US20240332153A1

公开(公告)日：2024-10-03

申请号：US18129880

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Tchefor NDUKUM ,  Yonggang LI ,  Rengarajan SHANMUGAM ,  Darko GRUJICIC ,  Deniz TURAN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49866

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate and a seed layer over the substrate. In an embodiment, sidewalls of the seed layer are sloped. In an embodiment, the electronic package further comprises a feature over the seed layer, where the feature is electrically conductive.

公开(公告)号：US20240096678A1

公开(公告)日：2024-03-21

申请号：US17949258

申请日：2022-09-21

Applicant: Intel Corporation

Inventor： Deniz TURAN ,  Yosef KORNBLUTH ,  Yonggang LI

IPC: H01L21/683 ,  H01L21/677

CPC classification number: H01L21/6833 ,  H01L21/67781

Abstract: The present disclosure is directed to a carrier chuck having a base plate with a top surface, at least one electrode positioned in a first carrier region of the top surface and configured to produce an electrostatic force to retain a panel placed on the carrier chuck during panel processing, and a dielectric layer positioned over the at least one electrode. The at least one electrode extends from the top surface by a height of at least 20 um.

公开(公告)号：US20240181572A1

公开(公告)日：2024-06-06

申请号：US18060578

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Tchefor NDUKUM ,  Deniz TURAN ,  Yonggang LI

IPC: B23K26/40 ,  B23K26/0622 ,  B23K26/082

CPC classification number: B23K26/40 ,  B23K26/0622 ,  B23K26/082 ,  B23K2101/40

Abstract: The present disclosure generally relates to a method. The method may include providing a substrate and forming a seed layer on the substrate. The method may further include forming a first metal layer on selected portions of the seed layer to form exposed portions of the seed layer. The method may also include scanning a laser beam across the substrate to remove the exposed portions of the seed layer to form exposed portions of the substrate.

公开(公告)号：US20240178157A1

公开(公告)日：2024-05-30

申请号：US18071257

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Vinith BEJUGAM ,  Whitney BRYKS ,  Brandon C. MARIN ,  Vishal Bhimrao ZADE ,  Deniz TURAN ,  Srinivas V. PIETAMBARAM

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49822

Abstract: Embodiments disclosed herein include package substrates. In a particular embodiment, the package substrate comprises a core. The core may be a glass core. In an embodiment, buildup layers are provided over the core, and a shape memory polymer (SMP) is provided over the core.