公开(公告)号：US20180068695A1

公开(公告)日：2018-03-08

申请号：US15703589

申请日：2017-09-13

Applicant: Intel Corporation

Inventor： Prashant S. DAMLE ,  Frank T. HADY ,  Paul D. RUBY ,  Kiran PANGAL ,  Sowmiya JAYACHANDRAN

IPC: G11C7/10 ,  G11C11/406 ,  G11C16/34

CPC classification number: G11C7/1072 ,  G11C11/406 ,  G11C11/40618 ,  G11C16/3431

Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

公开(公告)号：US20220415425A1

公开(公告)日：2022-12-29

申请号：US17358421

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Hemant P. RAO ,  Raymond W. ZENG ,  Prashant S. DAMLE ,  Zion S. KWOK ,  Kiran PANGAL ,  Mase J. TAUB

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/50 ,  G11C7/06

Abstract: A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.

公开(公告)号：US20210110862A1

公开(公告)日：2021-04-15

申请号：US17128963

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Akanksha MEHTA ,  Benjamin GRANIELLO ,  Rakan MADDAH ,  Philip HILLIER ,  Richard P. MANGOLD ,  Prashant S. DAMLE ,  Kunal A. KHOCHARE

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4076 ,  G11C15/04

Abstract: A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array. In this way, the subsequent write commands received during a time window after the first write command are coalesced and a single subsequent write command is sent to the memory.

公开(公告)号：US20190043571A1

公开(公告)日：2019-02-07

申请号：US15939026

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Prashant S. DAMLE ,  Wei FANG ,  Albert FAZIO

IPC: G11C13/00 ,  G06F13/16 ,  G06F13/40

Abstract: A memory device includes a memory array having multiple nonvolatile memory cells that stores data as a set or a reset state of the memory cells. The nonvolatile memory cells can be resistance-based memory, which stores data based on resistive state of the memory cells. A controller coupled to the memory array periodically samples set and reset margins for memory cells of the memory array. Responsive to detection of a change in a margin, the system can adaptively adjust a preset electrical setting used to differentiate between a set state and a reset state.

公开(公告)号：US20210193248A1

公开(公告)日：2021-06-24

申请号：US17132902

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Lunkai ZHANG ,  Rakan MADDAH ,  Prashant S. DAMLE

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/18 ,  G11C29/00

Abstract: A “near miss” based refresh scheme performs refreshes to read disturbed codewords proactively (or on-demand). In one example, a controller receives a read request to a target address (e.g., from a host memory controller). The read request is sent to memory, and the memory returns the read data. ECC logic decodes the read data and determines the number of error bits in the read data. If the number of error bits is greater than a threshold, a refresh write command is sent to the command queue. If an outstanding write command to the same address is already in the queue, the refresh write can be dropped and the outstanding write command converted into a refresh write command. A data cache can service read commands to the target address until the near miss-based refresh command completes.

公开(公告)号：US20180253355A1

公开(公告)日：2018-09-06

申请号：US15909929

申请日：2018-03-01

Applicant: Intel Corporation

Inventor： Kiran PANGAL ,  Prashant S. DAMLE ,  Rajesh SUNDARAM ,  Shekoufeh QAWAMI ,  Julie M. WALKER ,  Doyle RIVERS

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/27 ,  H03M13/05 ,  G06F3/06 ,  H03M13/15 ,  H03M13/19

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  H03M13/05 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/27 ,  H03M13/6508

Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.