公开(公告)号：US20240084456A1

公开(公告)日：2024-03-14

申请号：US18332117

申请日：2023-06-09

Applicant: Kioxia Corporation

Inventor： Kazuhiro KATONO ,  Kazuhiro MATSUO ,  Yusuke MIKI ,  Kenichiro TORATANI ,  Akifumi GAWASE

IPC: C23C16/52 ,  C23C16/40 ,  C23C16/455 ,  C23C16/458 ,  H01L21/02 ,  H01L21/66

CPC classification number: C23C16/52 ,  C23C16/407 ,  C23C16/45565 ,  C23C16/4584 ,  H01L21/02565 ,  H01L21/0262 ,  H01L22/20 ,  H01L21/02381

Abstract: In one embodiment, a film forming apparatus includes a chamber configured to load a substrate, a stage configured to support the substrate, and a gas supplier configured to supply a gas into the chamber to form a film on the substrate. The device further includes a first detector configured to detect a first value that varies depending on at least pressure of a first portion above the stage in the chamber, and a controller configured to control a process of forming the film on the substrate based on the first value.

公开(公告)号：US20230290882A1

公开(公告)日：2023-09-14

申请号：US17897050

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Ha HOANG ,  Kazuhiro MATSUO ,  Tomoki ISHIMARU ,  Kenichiro TORATANI

IPC: H01L29/786 ,  H01L27/108

CPC classification number: H01L29/78642 ,  H01L27/1082 ,  H01L29/78693

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, and an oxide semiconductor layer provided between the first electrode and the second electrode and including a first region, a second region between the first region and the second electrode, and a third region between the first region and the second region. A gate electrode surrounds the third region, and a gate insulating layer is between the gate electrode and the third region. A first resistivity of the first region is higher than a second resistivity of the second region. A first distance between the first electrode and the gate electrode in a first direction from the first electrode toward the second electrode is shorter than a second distance between the gate electrode and the second electrode in the first direction.

公开(公告)号：US20230088864A1

公开(公告)日：2023-03-23

申请号：US17687379

申请日：2022-03-04

Applicant: Kioxia Corporation

Inventor： Yuta KAMIYA ,  Kazuhiro MATSUO ,  Kota TAKAHASHI ,  Masaya TODA ,  Tomoki ISHIMARU

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor memory device according to an embodiment includes: a first oxide semiconductor layer between a first conductive layer and a second conductive layer; a first gate electrode; a first electrode; a second electrode; a first capacitor insulating film between the first electrode and the second electrode including a first region and a second region between the first region and the second electrode, concentration of the Ti is higher in the second region than the first region; a third conductive layer; a second oxide semiconductor layer between the third conductive layer and a fourth conductive layer; a second gate electrode; a third electrode; a fourth electrode; and a second capacitor insulating film between the third electrode and the fourth electrode, and including a third region and a fourth region between the third region and the fourth electrode, concentration of Ti is higher in the fourth region than the third region.

公开(公告)号：US20220336492A1

公开(公告)日：2022-10-20

申请号：US17850699

申请日：2022-06-27

Applicant: KIOXIA CORPORATION

Inventor： Yuta SAITO ,  Shinji MORI ,  Atsushi TAKAHASHI ,  Toshiaki YANASE ,  Keiichi SAWA ,  Kazuhiro MATSUO ,  Hiroyuki YAMASHITA

IPC: H01L27/11582 ,  H01L21/02 ,  H01L29/04

Abstract: In one embodiment, a semiconductor storage device includes a stacked body in which a plurality of conducting layers are stacked through a plurality of insulating layers in a first direction, a semiconductor layer penetrating the stacked body, extending in the first direction and including metal atoms, and a memory film including a first insulator, a charge storage layer and a second insulator that are provided between the stacked body and the semiconductor layer. The semiconductor layer surrounds a third insulator penetrating the stacked body and extending in the first direction, and at least one crystal grain in the semiconductor layer has a shape surrounding the third insulator.

公开(公告)号：US20220302169A1

公开(公告)日：2022-09-22

申请号：US17411733

申请日：2021-08-25

Applicant: KIOXIA CORPORATION

Inventor： Keisuke TAKAGI ,  Kazuhiro MATSUO ,  Kunifumi SUZUKI ,  Yuuichi KAMIMUTA ,  Taro SHIOKAWA ,  Masumi SAITOH ,  Yuta KAMIYA ,  Kota TAKAHASHI

IPC: H01L27/11597 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor storage device includes a channel layer extending along a first direction and including titanium oxide, an electrode layer extending along a second direction crossing the first direction, and a ferroelectric layer between the channel layer and the electrode layer and including titanium.

公开(公告)号：US20210305431A1

公开(公告)日：2021-09-30

申请号：US17022328

申请日：2020-09-16

Applicant: Kioxia Corporation

Inventor： Tomoki ISHIMARU ,  Shinji MORI ,  Kazuhiro MATSUO ,  Keiichi SAWA ,  Akifumi GAWASE

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/08 ,  H01L29/417 ,  H01L29/40 ,  H01L29/267

Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, a first metallic region provided between the first electrode and the second electrode and includes at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), magnesium (Mg), manganese (Mn), titanium (Ti), tungsten (W), molybdenum (Mo), and tin (Sn), a second metallic region provided between the first metallic region and the second electrode and includes the at least one metallic element, a semiconductor region provided between the first metallic region and the second metallic region and includes the at least one metallic element and oxygen (O), an insulating region provided between the first metallic region and the second metallic region and is surrounded by the semiconductor region, a gate electrode surrounding the semiconductor region, and a gate insulating layer provided between the semiconductor region and the gate electrode.

公开(公告)号：US20250098248A1

公开(公告)日：2025-03-20

申请号：US18828277

申请日：2024-09-09

Applicant: Kioxia Corporation

Inventor： Masaya NAKATA ,  Kota TAKAHASHI ,  Yusuke MIKI ,  Takuma DOI ,  Kazuhiro MATSUO ,  Akifumi GAWASE ,  Kenichiro TORATANI

IPC: H01L29/26 ,  C23C16/52 ,  H01J37/32 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/66

Abstract: A semiconductor device manufacturing method of embodiments includes: forming a first conductive film containing indium on a substrate; forming a first insulating film; forming a second conductive film; forming a second insulating film; forming an opening penetrating the second insulating film, the second conductive film, and the first insulating film to reach the first conductive film; forming a third insulating film in the opening so as to be in contact with bottom and side surfaces of the opening; removing the third insulating film at a bottom of the opening to expose the first conductive film at the bottom of the opening; performing a first treatment using a first gas containing silicon or a second treatment using a second gas containing oxygen; and forming a semiconductor film in the opening without exposing the substrate to an atmosphere with a pressure equal to or more than atmospheric pressure.

公开(公告)号：US20240421071A1

公开(公告)日：2024-12-19

申请号：US18743245

申请日：2024-06-14

Applicant: Kioxia Corporation

Inventor： Ha HOANG ,  Kazuhiro MATSUO ,  Mutsumi OKAJIMA ,  Takamitsu OCHI ,  Tsuyoshi SUGISAKI ,  Isamu UJIIE

IPC: H01L23/522 ,  G11C5/06 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor memory device includes a plurality of memory layers arranged in a first direction, a first via-wiring extending in the first direction, a second via-wiring in a position different from a position of the first via-wiring in a second direction and extending in the first direction. One of the plurality of memory layers includes a first wiring disposed between the first and the second via-wiring and extending in a third direction, a first semiconductor layer electrically connected to the first via-wiring, a first gate electrode opposed to the first semiconductor layer and electrically connected to the first wiring, a first memory portion electrically connected to the first semiconductor layer, a second semiconductor layer electrically connected to the second via-wiring, a second gate electrode opposed to the second semiconductor layer and electrically connected to the first wiring, and a second memory portion electrically connected to the second semiconductor layer.

公开(公告)号：US20230402548A1

公开(公告)日：2023-12-14

申请号：US18052957

申请日：2022-11-07

Applicant: Kioxia Corporation

Inventor： Ha HOANG ,  Kazuhiro MATSUO ,  Kenichiro TORATANI

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78696

Abstract: In general, according to one embodiment, a semiconductor device includes first to third conductors, a semiconductor, a first insulator, and an insulation region. The semiconductor includes a metal oxide and extends in the first direction to be in contact with the first conductor and the third conductor. The insulation region is surrounded by the semiconductor and extends in the first direction to be in contact with the first conductor. The semiconductor includes a first portion and a second portion defined between the first portion and the insulation region. A concentration of a first element contained in the metal oxide of the semiconductor is higher in the second portion than in the first portion.

公开(公告)号：US20230200050A1

公开(公告)日：2023-06-22

申请号：US17841129

申请日：2022-06-15

Applicant: Kioxia Corporation

Inventor： Akifumi GAWASE ,  Ha HOANG ,  Atsuko SAKATA ,  Yuta KAMIYA ,  Kazuhiro MATSUO ,  Keiichi SAWA ,  Kota TAKAHASHI ,  Kenichiro TORATANI ,  Yimin LIU

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/10805 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/66969 ,  H01L27/10873

Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; an oxide semiconductor layer between the first electrode and the second electrode; a gate electrode surrounding the oxide semiconductor layer; a gate insulating layer between the gate electrode and the oxide semiconductor layer; a first insulating layer provided between the first electrode and the gate electrode; and a second insulating layer provided between the second electrode and the gate electrode. In a cross section parallel to a first direction from the first electrode to the second electrode, a first portion of the oxide semiconductor layer is provided between the gate insulating layer and the first electrode. In the cross section, a second portion of the oxide semiconductor layer is provided between the gate insulating layer and the second electrode.