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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US12211551B2

    公开(公告)日：2025-01-28

    申请号：US18177704

    申请日：2023-03-02

    Applicant: Kioxia Corporation

    Inventor： Natsuki Sakaguchi ,  Takashi Maeda ,  Rieko Funatsuki ,  Hidehiro Shiga

    IPC: G11C16/04 ,  G11C7/06 ,  G11C16/24

    Abstract: A control circuit of a semiconductor memory device performs a write operation on a memory cell transistor of the semiconductor memory device by performing a first pulse application operation of lowering a threshold voltage of the memory cell transistor, a precharge operation, and then a second pulse application operation. In the precharge operation, in a state in which first and second select transistors connected to the memory cell transistor are turned on, a bit line connected to the memory cell transistor is charged by applying a ground voltage to a word line connected to a gate of the memory cell transistor and applying a voltage higher than the ground voltage to a source line. In the second pulse application operation, in a state in which the first select transistor is turned on and the second select transistor is turned off, a program voltage is applied to the word line.

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US12159040B2

    公开(公告)日：2024-12-03

    申请号：US17899974

    申请日：2022-08-31

    Applicant: KIOXIA CORPORATION

    Inventor： Rieko Funatsuki ,  Takashi Maeda ,  Sumiko Domae ,  Kazutaka Ikegami

    IPC: G06F3/06

    Abstract: A semiconductor memory device includes a semiconductor pillar including first and second memory cells electrically connected in series and formed on opposite sides of the semiconductor pillar, first word lines connected to the first memory cells, respectively, and second word lines connected to the second memory cells, respectively. A verify operation includes a channel clean operation for supplying a reference voltage to a semiconductor channel shared by the first and second memory cells followed by at least first and second sense operation for determining whether a threshold voltage of a target memory cell has reached first and second threshold voltage states, respectively, then a second channel clean operation for supplying the reference voltage to the semiconductor channel, and then at least a third sense operation for determining whether the threshold voltage of the target memory cell has reached a third threshold voltage state.

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11967371B2

    公开(公告)日：2024-04-23

    申请号：US17806346

    申请日：2022-06-10

    Applicant: Kioxia Corporation

    Inventor： Rieko Funatsuki ,  Takashi Maeda ,  Hidehiro Shiga

    IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

    CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459

    Abstract: A semiconductor memory device includes i first word lines connected to the i first memory cells, i second word lines connected to the i second memory cells, a driver capable of supplying voltage to each of the i first word lines and each of the i second word lines, and a logic control circuit controlling both a write operation including a verify operation and a read operation including a verify operation. In the semiconductor memory device, when an order of performing a sense operation for determining whether or not a threshold voltage of the k-th first memory cell has reached a j-th threshold voltage in the verify operation is different from that of in the read operation, a voltage applied to the k-th first word line in the verify operation is different from a voltage applied to the k-th first word line in the read operation.

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US12211557B2

    公开(公告)日：2025-01-28

    申请号：US18176507

    申请日：2023-03-01

    Applicant: Kioxia Corporation

    Inventor： Kyosuke Sano ,  Kazutaka Ikegami ,  Takashi Maeda

    IPC: G11C16/14 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  H10B41/35 ,  H10B41/41

    Abstract: A semiconductor memory device includes a first memory pillar and a sequencer. The first memory pillar is sandwiched between a first word line and a second word line, sandwiched between a third word line and a fourth word line, sandwiched between a fifth word line and a sixth word line, includes a first memory cell facing the first word line, a second memory cell facing the second word line, a third memory cell facing the third word line, a fourth memory cell facing the fourth word line, a fifth memory cell facing the fifth word line and a sixth memory cell facing the sixth word line. The sequencer executes an erase operation on the first to sixth memory cells to enable execution of a primary write operation for the first memory cell and a primary write operation for the second memory cell at different timings.

    Semiconductor storage apparatus including a memory cell array
    10.
    发明授权
    Semiconductor storage apparatus including a memory cell array 有权

    公开(公告)号：US11282578B2

    公开(公告)日：2022-03-22

    申请号：US16906140

    申请日：2020-06-19

    Applicant: Kioxia Corporation

    Inventor： Rieko Funatsuki ,  Takahiko Hara ,  Takashi Maeda

    IPC: G11C16/26 ,  G11C16/04 ,  H01L27/115

    Abstract: A semiconductor storage apparatus includes a memory cell array including a plurality of memory string structures each including a pair of memory string formation sections each formed by a channel formation film and a charge storage film and including a select gate transistor and a plurality of memory cell transistors connected in series and a partial conductive layer configured to electrically connect the memory string formation sections. During a reading operation of a memory cell transistor, at least one of the plurality of memory cell transistors and the select gate transistor belonging to the memory string formation section is turned off such that a channel of a memory cell transistor is fixed to a potential of a source line or a potential of bit lines.

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