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公开(公告)号:US20250141961A1
公开(公告)日:2025-05-01
申请号:US19012523
申请日:2025-01-07
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Adi Merav Horowitz , Rabia Loulou , Omri Kahalon , Gal Shalom , Aviad Yehezkel , Asaf Schwartz , Liran Liss
IPC: H04L67/1097 , H04L67/146
Abstract: Systems and methods enable session sharing for session-based remote direct memory access (RDMA). Multiple queue pairs (QPs) can be added to a single session and/or session group where each of the QPs has a common remote. Systems and methods may query a session ID for an existing session group and then use the session ID with an add QP request to join additional QPs to an existing session. Newly added QPs may share one or more features with existing QPs of the session group, such as encryption parameters. Additionally, newly added QPs may be configured with different performance or quality of service requirements, thereby isolating performance, and permitting true scaling for high performance computing applications.
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公开(公告)号:US20250123980A1
公开(公告)日:2025-04-17
申请号:US18988345
申请日:2024-12-19
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Daniel Marcovitch , Liran Liss , Rabia Loulou , Aviad Yehezkel
IPC: G06F13/24 , G06F13/40 , G06F13/42 , G06F15/173
Abstract: Methods, systems, and devices for message signaled interrupt (MSI-X) tunneling on a host device exposed by a bridge connection are described. A device may receive data and a first interrupt signal from a remote destination over a network protocol. The device may receive the data and/or the first interrupt signal over the bridge connection, via a tunneled communication from the remote destination. The device may generate a second interrupt signal based on the first interrupt signal and a local interrupt configuration provided by a system bus driver of the device. The device may inject the data and the second interrupt signal over the system bus. Injecting the data and injecting the second interrupt signal may include ensuring the data is made available to the system bus driver, prior to the interrupt handler receiving the second interrupt signal.
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公开(公告)号:US12259832B2
公开(公告)日:2025-03-25
申请号:US18174668
申请日:2023-02-27
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Tzahi Oved , Achiad Shochat , Liran Liss , Noam Bloch , Aviv Heller , Idan Burstein , Ariel Shahar , Peter Paneah
Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.
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公开(公告)号:US20240259233A1
公开(公告)日:2024-08-01
申请号:US18162938
申请日:2023-02-01
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Gal Shalom , Omri Kahalon , Adi Horowitz , Aviad Yehezkel , Liran Liss , Rabia Loulou , Matty Kadosh
IPC: H04L12/46 , H04L12/66 , H04L49/351 , H04L49/356
CPC classification number: H04L12/4625 , H04L12/66 , H04L49/351 , H04L49/358
Abstract: Systems and methods herein are for one or more processing units to modify a network access layer of an ethernet communication to include a local route header (LRH) of an InfiniBand (IB) communication for transmission over an IB network, the modification further to retain ethernet information of all layers of the ethernet communication or to remove at least one of the layers of the ethernet communication for the IB communication.
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5.
公开(公告)号:US12045178B2
公开(公告)日:2024-07-23
申请号:US17673105
申请日:2022-02-16
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Dimitrios Syrivelis , Paraskevas Bakopoulos , Ioannis (Giannis) Patronas , Elad Mentovich , James Stephen Fields, Jr. , Haggai Eran , Liran Liss
IPC: G06F13/16
CPC classification number: G06F13/1642
Abstract: A system comprises a first processing block configured to receive, from a first local resource, a formatted transaction in a format that is not recognizable by a remote endpoint; determine a first transaction category, from among a plurality of transaction categories, of the formatted transaction based on content of the formatted transaction; perform one or operations on the formatted transaction based on the first transaction category to form a reformatted transaction in a format that is recognizable by the remote endpoint; and place the reformatted transaction in a queue for transmission to the remote endpoint.
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公开(公告)号:US11940935B2
公开(公告)日:2024-03-26
申请号:US17234189
申请日:2021-04-19
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Eliav Bar-Ilan , Oren Duer , Maxim Gurtovoy , Liran Liss , Aviad Shaul Yehezkel
IPC: G06F13/28 , G06F9/455 , G06F13/42 , G06F15/173
CPC classification number: G06F13/28 , G06F9/45558 , G06F13/4221 , G06F13/4282 , G06F15/17331 , G06F2009/45583 , G06F2213/0024 , G06F2213/0026
Abstract: A computerized system operating in conjunction with computerized apparatus and with a fabric target service in data communication with the computerized apparatus, the system comprising functionality residing on the computerized apparatus, and functionality residing on the fabric target service, which, when operating in combination, enable the computerized apparatus to coordinate access to data.
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公开(公告)号:US11765237B1
公开(公告)日:2023-09-19
申请号:US17724540
申请日:2022-04-20
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Liran Liss , Yamin Friedman , Michael Kagan , Diego Crupnicoff , Idan Burstein , Matty Kadosh , Tzah Oved , Dror Goldenberg , Ron Yuval Efraim , Alexander Eli Rosenbaum , Aviad Yehezkel , Rabia Loulou
IPC: H04L67/141 , H04L67/146 , G06F15/173 , H04L69/16 , H04L9/08
CPC classification number: H04L67/141 , G06F15/17331 , H04L9/0825 , H04L67/146 , H04L69/161
Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.
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8.
公开(公告)号:US20230269003A1
公开(公告)日:2023-08-24
申请号:US17675669
申请日:2022-02-18
Applicant: Mellanox Technologies, Ltd.
Inventor: Juan Jose Vegas Olmos , Elad Mentovich , Liran Liss , Yonathan Piasetzky
Abstract: Embodiments are disclosed for facilitating quantum computing over classical and quantum communication channels. An example system includes a network interface card (NIC) apparatus. The NIC apparatus includes an optical receiver, an embedded processor, and a network switch. The optical receiver is configured to receive qubit data via a first communication channel associated with quantum communication. The embedded processor is configured to convert the qubit data into binary bit data. The network switch is configured to output the binary bit data via a second communication channel associated with classical network communication.
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公开(公告)号:US20230133439A1
公开(公告)日:2023-05-04
申请号:US17536141
申请日:2021-11-29
Applicant: Mellanox Technologies, Ltd.
Inventor: Ran Avraham Koren , Ariel Shahar , Liran Liss , Gabi Liron , Aviad Shaul Yehezkel
IPC: G06F12/0882 , G06F12/0831 , G06F13/16
Abstract: A compute node includes a memory, a processor and a peripheral device. The memory is to store memory pages. The processor is to run software that accesses the memory, and to identify one or more first memory pages that are accessed by the software in the memory. The peripheral device is to directly access one or more second memory pages in the memory of the compute node using Direct Memory Access (DMA), and to notify the processor of the second memory pages that are accessed using DMA. The processor is further to maintain a data structure that tracks both (i) the first memory pages as identified by the processor and (ii) the second memory pages as notified by the peripheral device.
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公开(公告)号:US20210203610A1
公开(公告)日:2021-07-01
申请号:US17204968
申请日:2021-03-18
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Boris Pismenny , Liran Liss , Ilya Lesokhin , Haggai Eran , Adi Menachem
IPC: H04L12/833 , H04L29/06 , H04L12/931 , H04L29/08 , H04L12/851 , H04L12/413 , H04L12/00
Abstract: Apparatus including a first interface to a host processor, a second interface to transmit and receive data packets having headers and payloads, to and from a packet communication network, a memory holding context information regarding a flow of the data and assigning serial numbers to the data packets in the flow, according to a session-layer protocol, and processing circuitry between the first and second interfaces and having acceleration logic, to decode the data records according to the session-layer protocol, using and updating the context information based on the serial numbers and the data records of the received packets, and processing circuitry writing the decoded data records through the first interface to a host memory. The acceleration logic, upon receiving in a given flow a data packet containing a serial number that is out of order, reconstructs the context information and applies that context information in decoding data records in subsequent data packets in the flow.
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