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    SESSION SHARING WITH REMOTE DIRECT MEMORY ACCESS CONNECTIONS
    1.
    发明申请
    SESSION SHARING WITH REMOTE DIRECT MEMORY ACCESS CONNECTIONS 有权

    公开(公告)号：US20250141961A1

    公开(公告)日：2025-05-01

    申请号：US19012523

    申请日：2025-01-07

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Adi Merav Horowitz ,  Rabia Loulou ,  Omri Kahalon ,  Gal Shalom ,  Aviad Yehezkel ,  Asaf Schwartz ,  Liran Liss

    IPC: H04L67/1097 ,  H04L67/146

    Abstract: Systems and methods enable session sharing for session-based remote direct memory access (RDMA). Multiple queue pairs (QPs) can be added to a single session and/or session group where each of the QPs has a common remote. Systems and methods may query a session ID for an existing session group and then use the session ID with an add QP request to join additional QPs to an existing session. Newly added QPs may share one or more features with existing QPs of the session group, such as encryption parameters. Additionally, newly added QPs may be configured with different performance or quality of service requirements, thereby isolating performance, and permitting true scaling for high performance computing applications.

    INTERRUPT EMULATION ON NETWORK DEVICES
    2.
    发明申请
    INTERRUPT EMULATION ON NETWORK DEVICES 有权

    公开(公告)号：US20250123980A1

    公开(公告)日：2025-04-17

    申请号：US18988345

    申请日：2024-12-19

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Daniel Marcovitch ,  Liran Liss ,  Rabia Loulou ,  Aviad Yehezkel

    IPC: G06F13/24 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

    Abstract: Methods, systems, and devices for message signaled interrupt (MSI-X) tunneling on a host device exposed by a bridge connection are described. A device may receive data and a first interrupt signal from a remote destination over a network protocol. The device may receive the data and/or the first interrupt signal over the bridge connection, via a tunneled communication from the remote destination. The device may generate a second interrupt signal based on the first interrupt signal and a local interrupt configuration provided by a system bus driver of the device. The device may inject the data and the second interrupt signal over the system bus. Injecting the data and injecting the second interrupt signal may include ensuring the data is made available to the system bus driver, prior to the interrupt handler receiving the second interrupt signal.

    Multi-socket network interface controller with consistent transaction ordering
    3.
    发明授权
    Multi-socket network interface controller with consistent transaction ordering 有权

    公开(公告)号：US12259832B2

    公开(公告)日：2025-03-25

    申请号：US18174668

    申请日：2023-02-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

    IPC: G06F13/28 ,  G06F3/06

    Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

    Memory Access Tracking Using a Peripheral Device
    9.
    发明申请
    Memory Access Tracking Using a Peripheral Device 有权

    公开(公告)号：US20230133439A1

    公开(公告)日：2023-05-04

    申请号：US17536141

    申请日：2021-11-29

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Ran Avraham Koren ,  Ariel Shahar ,  Liran Liss ,  Gabi Liron ,  Aviad Shaul Yehezkel

    IPC: G06F12/0882 ,  G06F12/0831 ,  G06F13/16

    Abstract: A compute node includes a memory, a processor and a peripheral device. The memory is to store memory pages. The processor is to run software that accesses the memory, and to identify one or more first memory pages that are accessed by the software in the memory. The peripheral device is to directly access one or more second memory pages in the memory of the compute node using Direct Memory Access (DMA), and to notify the processor of the second memory pages that are accessed using DMA. The processor is further to maintain a data structure that tracks both (i) the first memory pages as identified by the processor and (ii) the second memory pages as notified by the peripheral device.

    Computational accelerator for packet payload operations
    10.
    发明申请
    Computational accelerator for packet payload operations 有权

    公开(公告)号：US20210203610A1

    公开(公告)日：2021-07-01

    申请号：US17204968

    申请日：2021-03-18

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Boris Pismenny ,  Liran Liss ,  Ilya Lesokhin ,  Haggai Eran ,  Adi Menachem

    IPC: H04L12/833 ,  H04L29/06 ,  H04L12/931 ,  H04L29/08 ,  H04L12/851 ,  H04L12/413 ,  H04L12/00

    Abstract: Apparatus including a first interface to a host processor, a second interface to transmit and receive data packets having headers and payloads, to and from a packet communication network, a memory holding context information regarding a flow of the data and assigning serial numbers to the data packets in the flow, according to a session-layer protocol, and processing circuitry between the first and second interfaces and having acceleration logic, to decode the data records according to the session-layer protocol, using and updating the context information based on the serial numbers and the data records of the received packets, and processing circuitry writing the decoded data records through the first interface to a host memory. The acceleration logic, upon receiving in a given flow a data packet containing a serial number that is out of order, reconstructs the context information and applies that context information in decoding data records in subsequent data packets in the flow.

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