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    Memory array with compensated word line access delay
    1.
    发明授权
    Memory array with compensated word line access delay 有权

    公开(公告)号：US12080330B2

    公开(公告)日：2024-09-03

    申请号：US17899859

    申请日：2022-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Si Hong Kim ,  John D. Porter

    IPC: G11C11/22

    CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2257

    Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.

    SENSING A MEMORY CELL
    3.
    发明申请
    SENSING A MEMORY CELL 有权

    公开(公告)号：US20210383856A1

    公开(公告)日：2021-12-09

    申请号：US17409608

    申请日：2021-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Huy T. Vo ,  Adam S. El-Mansouri ,  Suryanarayana B. Tatapudi ,  John D. Porter

    IPC: G11C11/22

    Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

    Wear leveling
    4.
    发明授权
    Wear leveling 有权

    公开(公告)号：US11056157B2

    公开(公告)日：2021-07-06

    申请号：US16856562

    申请日：2020-04-23

    Applicant: Micron Technology, Inc.

    Inventor： John D. Porter

    IPC: G11C7/10 ,  G06F12/02 ,  G11C11/22

    Abstract: An apparatus has a controller and an array of memory cells, including a first section comprising a plurality of rows and a second section comprising a plurality of rows. The controller configured to, in association with wear leveling, transfer data stored in a first row of the first section from the first row to a register, transfer the data from the register to a destination row of the second section while data in a second row of the first section is being sensed.

    Temperature-based access timing for a memory device
    6.
    发明授权
    Temperature-based access timing for a memory device 有权

    公开(公告)号：US10978130B1

    公开(公告)日：2021-04-13

    申请号：US16829996

    申请日：2020-03-25

    Applicant: Micron Technology, Inc.

    Inventor： Victor Wong ,  Sihong Kim ,  Hiroshi Akamatsu ,  Daniele Vimercati ,  John D. Porter

    IPC: G11C7/04 ,  G11C11/22

    Abstract: Methods, systems, and devices for temperature-based access timing for a memory device are described. In some memory devices, accessing memory cells may be associated with different operations that are variously dependent on a temperature of the memory device. For example, some operations associated with accessing a memory cell may have a longer duration and others a shorter duration depending on the temperature of the memory device. In accordance with examples as disclosed herein, a memory device may be configured for performing some portions of an access operation according to a duration that is proportional to a temperature of the memory device, and performing other portions of the access operation according to a duration that is inversely proportional to a temperature of the memory device.

    Method and apparatus for reducing impact of transistor random mismatch in circuits
    8.
    发明授权
    Method and apparatus for reducing impact of transistor random mismatch in circuits 有权

    公开(公告)号：US10320371B2

    公开(公告)日：2019-06-11

    申请号：US16121237

    申请日：2018-09-04

    Applicant: Micron Technology, Inc.

    Inventor： Dong Pan ,  John D. Porter

    IPC: H03K5/007 ,  H03K5/156 ,  H03K17/16 ,  H03F3/45 ,  H03M3/00

    Abstract: An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

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