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    Memory disturb reduction for nonvolatile memory
    4.
    发明授权
    Memory disturb reduction for nonvolatile memory 有权
    非易失性存储器的存储器干扰减少

    公开(公告)号：US09025375B2

    公开(公告)日：2015-05-05

    申请号：US14060296

    申请日：2013-10-22

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsing-Chen Lu ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G11C16/04 ,  G11C16/34 ,  G06F12/02

    CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3427

    Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.

    Abstract translation: 描述了支持减少非易失性存储器的程序干扰的技术。 三/二维NAND阵列包括被分成多个页组的多页。 允许访问在三维NAND阵列的擦除块中的多个寻呼组的第一页组内的存储单元，同时访问最小化到擦除块中的多个页组的第二页组内的存储单元 的三/二维NAND阵列。 同一页组中的页面在三维/二维NAND阵列中彼此物理上不相邻。

    Memory device and operation method thereof
    6.
    发明授权
    Memory device and operation method thereof 有权

    公开(公告)号：US11640255B2

    公开(公告)日：2023-05-02

    申请号：US17518624

    申请日：2021-11-04

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Wei-Chen Wang ,  Ting-Hsuan Lo ,  Chun-Feng Wu ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G06F12/00 ,  G06F3/06

    Abstract: Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.

    Memory device for neural networks
    7.
    发明授权
    Memory device for neural networks 有权

    公开(公告)号：US11526285B2

    公开(公告)日：2022-12-13

    申请号：US16564066

    申请日：2019-09-09

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Wei-Chen Wang ,  Hung-Sheng Chang ,  Chien-Chung Ho ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G06F3/06 ,  G06N3/04

    Abstract: A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.

    Management system for managing memory device and management method for managing the same
    8.
    发明授权
    Management system for managing memory device and management method for managing the same 审中-公开

    公开(公告)号：US10671296B2

    公开(公告)日：2020-06-02

    申请号：US15672430

    申请日：2017-08-09

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Hung-Sheng Chang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G06F3/06 ,  G06F12/02 ,  G11C7/04

    Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.

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