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公开(公告)号:US20140177625A1
公开(公告)日:2014-06-26
申请号:US13722951
申请日:2012-12-20
CPC分类号: G02B6/43 , H01L2224/73204 , Y10T29/49117 , Y10T29/4913
摘要: Embodiments of the present disclosure provide techniques and configurations for routing signals of an electro-optical assembly using a glass bridge. In one embodiment, an electro-optical assembly includes a laser die having a laser device and a glass bridge electrically coupled with the laser die by one or more interconnect structures, the glass bridge including electrical routing features configured to route electrical signals to the laser die from a transmitter device. Other embodiments may be described and/or claimed.
摘要翻译: 本公开的实施例提供了使用玻璃桥路由电光学组件路由信号的技术和配置。 在一个实施例中,电光学组件包括具有激光器件的激光器管芯和通过一个或多个互连结构与激光管芯电耦合的玻璃桥,所述玻璃桥接器包括被配置为将电信号路由到激光器管芯 从发射机设备。 可以描述和/或要求保护其他实施例。
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公开(公告)号:US07068892B1
公开(公告)日:2006-06-27
申请号:US11096504
申请日:2005-03-29
申请人: Daoqiang Lu , Henning Braunisch , Edris M. Mohammed , Ian Young
发明人: Daoqiang Lu , Henning Braunisch , Edris M. Mohammed , Ian Young
IPC分类号: G02B6/42
CPC分类号: G02B6/4292 , G02B6/423 , G02B6/4232 , G02B6/4249
摘要: An optical-electrical interface includes an alignment interface and an optoelectronic die. The alignment interface is mounted to a substrate and includes a waveguide port to receive an external waveguide from a first side. The alignment interface includes a conductor disposed on a second side of the alignment interface to couple to a conductor on the substrate. The optoelectronic die is mounted to the second side of the alignment interface. The optoelectronic die includes an electrical port coupled to the conductor disposed on the alignment interface, an optoelectronic device coupled to the electrical port and an optical port aligned to optically couple the optoelectronic device to the external waveguide through the alignment interface.
摘要翻译: 光电接口包括对准接口和光电管芯。 对准接口安装到基板并且包括用于从第一侧接收外部波导的波导端口。 对准接口包括设置在对准接口的第二侧上的导体,以耦合到衬底上的导体。 光电管芯安装在对准接口的第二侧。 光电管芯包括耦合到布置在对准接口上的导体的电端口,耦合到电端口的光电子器件和对准以通过对准接口将光电子器件光耦合到外部波导的光端口。
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公开(公告)号:US20220413237A1
公开(公告)日:2022-12-29
申请号:US17359447
申请日:2021-06-25
申请人: Henning Braunisch , Adel Elsherbini
发明人: Henning Braunisch , Adel Elsherbini
IPC分类号: G02B6/42
摘要: Apparatus and methods of manufacture are disclosed. In one example the apparatus includes a first substrate that has a first surface, a first optical waveguide that is at or near the first surface of the first substrate, a second substrate that has a second surface. The second substrate is coupled to the first substrate at an interface. The apparatus also has a photonic integrated circuit (PIC) with a portion at or near the second surface. The PIC is in alignment with and optically coupled to the first optical waveguide across the interface.
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公开(公告)号:US20140120696A1
公开(公告)日:2014-05-01
申请号:US14146877
申请日:2014-01-03
IPC分类号: H01L21/78
CPC分类号: H01L21/78 , H01L22/32 , H01L23/52 , H01L23/585 , H01L24/05 , H01L24/16 , H01L2224/0401 , H01L2224/0557 , H01L2224/16145 , H01L2924/00014 , H01L2924/01019 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要: The present disclosure relates to the field of microelectronic die packaging, particularly multi-chip packaging, wherein on-substrate modularity is enabled by using in-street die-to-die interconnects to facilitate signal routing between microelectronic dice. These in-street die-to-die interconnects may allow for manufacturing of several products on a single microelectronic substrate, which may lead to improved microelectronic die and/or microelectronic module harvesting and increased product yields.
摘要翻译: 本公开内容涉及微电子管芯封装领域,特别是多芯片封装,其中通过使用街道芯片间管芯互连以实现微电子管芯之间的信号路由,能够实现基板上的模块化。 这些在街头的模 - 芯互连可以允许在单个微电子衬底上制造几个产品,这可以导致改进的微电子管芯和/或微电子模块收获和增加的产品产量。
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公开(公告)号:US20110247195A1
公开(公告)日:2011-10-13
申请号:US13167902
申请日:2011-06-24
申请人: Henning Braunisch , Kemal Aygun
发明人: Henning Braunisch , Kemal Aygun
IPC分类号: H01S4/00
CPC分类号: H05K1/0243 , H01L23/367 , H01L23/66 , H01L24/16 , H01L25/0657 , H01L25/16 , H01L2223/6622 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2225/06517 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/14 , H05K1/182 , H05K3/222 , H05K2201/10356 , H05K2201/10492 , H05K2201/10704 , Y10T29/49002 , H01L2924/00 , H01L2224/0401
摘要: A multimode system with at least two end points may include a multimode signaling path that, in some embodiments, is a multimode cable or a multimode board and is pluggably connectable to packages at each end point. Each end point may include a processor die package coupled to a socket. The socket may also receive a connector that couples the cable to the package. Power supply signals and input/output signals may be decoupled at each end point.
摘要翻译: 具有至少两个端点的多模系统可以包括在一些实施例中是多模电缆或多模板并且可插拔地连接到每个端点处的封装的多模信令路径。 每个端点可以包括耦合到插座的处理器管芯封装。 插座还可以接收将电缆耦合到封装的连接器。 电源信号和输入/输出信号可以在每个端点去耦。
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公开(公告)号:US07720337B2
公开(公告)日:2010-05-18
申请号:US12004541
申请日:2007-12-20
申请人: Daoqiang Lu , Henning Braunisch
发明人: Daoqiang Lu , Henning Braunisch
IPC分类号: G02B6/36
CPC分类号: G02B6/4231
摘要: In general, in one aspect, a method includes forming conductive layers on a wafer. A through cavity is formed in alignment with the conductive layers. The through cavity is to permit an optical signal from an optical waveguide within an optical connector to pass therethrough. Alignment holes are formed on each side of the through cavity to receive alignment pins. The wafer having the conductive layers, the through cavity in alignment with the conductive layers, and the alignment holes on each side of the through cavity forms an optical-electrical (O/E) interface. An O/E converter is mounted to the metal layers in alignment with the through cavity. The alignment pins and the alignment holes are used to passively align the optical waveguide and the O/E converter.
摘要翻译: 通常,一方面,一种方法包括在晶片上形成导电层。 形成与导电层对准的通孔。 通孔是允许光连接器内的光波导的光信号通过。 对准孔形成在通孔的每一侧以接收对准销。 具有导电层的晶片,与导电层对准的通孔和通孔的每一侧上的对准孔形成光电(O / E)界面。 O / E转换器安装到与通孔对准的金属层上。 对准引脚和对准孔用于被动对准光波导和O / E转换器。
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公开(公告)号:US20080228964A1
公开(公告)日:2008-09-18
申请号:US11717568
申请日:2007-03-13
申请人: Henning Braunisch
发明人: Henning Braunisch
IPC分类号: G06F3/00
CPC分类号: G06F1/18 , H05K1/14 , H05K1/147 , H05K3/222 , H05K2201/044 , H05K2201/10189 , H05K2201/10356 , H05K2201/10734
摘要: A hybrid memory interconnect system involving flexible cable and board interconnects is provided for improved memory bandwidth and power efficiency performance. To this purpose, signals between a microprocessor chip and one or more memory chips are routed via separate conductive paths, e.g. flexible cable for high-speed signals and conventional board interconnects for low-speed signals. The memory chips may be connected to a flexible cable and a supporting printed circuit board in various ways.
摘要翻译: 提供了涉及柔性电缆和电路板互连的混合存储器互连系统,用于改善存储器带宽和功率效率性能。 为此,微处理器芯片和一个或多个存储器芯片之间的信号经由分离的导电路径路由,例如, 用于高速信号的柔性电缆和用于低速信号的常规电路板互连。 存储器芯片可以以各种方式连接到柔性电缆和支撑印刷电路板。
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公开(公告)号:US20080153207A1
公开(公告)日:2008-06-26
申请号:US12044239
申请日:2008-03-07
申请人: Daoqiang Lu , Henning Braunisch
发明人: Daoqiang Lu , Henning Braunisch
IPC分类号: H01L21/00
CPC分类号: H01L23/49827 , H01L21/485 , H01L23/5382 , H01L24/28 , H01L24/83 , H01L2224/2919 , H01L2224/838 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/14 , H05K3/323 , H05K3/365 , H05K2201/0221 , H05K2201/0233 , H05K2201/0314 , H01L2924/00
摘要: Methods of forming a microelectronic structure are described. Embodiments of those methods include placing an anisotropic conductive layer comprising at least one compliant conductive sphere on at least one interconnect structure disposed on a first substrate, applying pressure to contact the compliant conductive spheres to the at least one interconnect structure, removing a portion of the anisotropic conductive layer to expose at least one of the compliant conductive spheres; and then attaching a second substrate to the anisotropic conductive layer.
摘要翻译: 描述形成微电子结构的方法。 这些方法的实施例包括将包括至少一个顺应性导电球的各向异性导电层放置在设置在第一衬底上的至少一个互连结构上,施加压力以使柔性导电球接触至少一个互连结构, 各向异性导电层以暴露柔性导电球体中的至少一个; 然后将第二基板附着到各向异性导电层。
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公开(公告)号:US07344318B2
公开(公告)日:2008-03-18
申请号:US11386149
申请日:2006-03-22
申请人: Daoqiang Lu , Henning Braunisch , Bram Leader , Mark B. Trobough
发明人: Daoqiang Lu , Henning Braunisch , Bram Leader , Mark B. Trobough
CPC分类号: G02B6/4292 , G02B6/3885 , G02B6/423 , H01L2224/16225
摘要: A coupler is passively aligned over a substrate, wherein the coupler is laterally aligned to an optoelectronic (OE) device coupled to the substrate. The coupler is placed on the substrate, wherein the coupler is vertically aligned to the OE device. The coupler is fixed to the substrate.
摘要翻译: 耦合器在衬底上被动对准,其中耦合器横向对准耦合到衬底的光电子(OE)器件。 耦合器被放置在基板上,其中耦合器垂直对准OE设备。 耦合器固定在基板上。
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公开(公告)号:US20070126118A1
公开(公告)日:2007-06-07
申请号:US11292893
申请日:2005-12-02
申请人: Daoqiang Lu , Henning Braunisch
发明人: Daoqiang Lu , Henning Braunisch
CPC分类号: H05K3/301 , H01L23/49833 , H01L23/4985 , H01L24/16 , H01L24/73 , H01L2224/13 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/01079 , H01L2924/14 , H01L2924/15192 , H05K3/341 , H05K3/361 , H05K3/365 , H05K2201/10393 , H05K2203/048 , H01L2924/014
摘要: A substrate may receive an integrated circuit and a flex circuit on the same side in the same vertical direction. In addition, in some embodiments, a flex circuit adapter and the integrated circuit may be surface mounted in one operation.
摘要翻译: 衬底可以在同一垂直方向上的同一侧上接收集成电路和柔性电路。 此外,在一些实施例中,柔性电路适配器和集成电路可以在一个操作中被表面安装。
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