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公开(公告)号:US20200258557A1
公开(公告)日:2020-08-13
申请号:US16793638
申请日:2020-02-18
Applicant: Rambus Inc.
Inventor: Thomas GIOVANNINI , Scott C. BEST , Lei LUO , Ian SHAEFFER
Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.
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公开(公告)号:US20240146546A1
公开(公告)日:2024-05-02
申请号:US18278374
申请日:2022-02-25
Applicant: Rambus Inc.
Inventor: Scott C. BEST , Thomas VOGELSANG , Michael Alexander HAMBURG , Mark Evan MARSON , Helena HANDSCHUH , HAMPEL E. Craig , Kenneth Lee WRIGHT
CPC classification number: H04L9/3268 , G06F21/73
Abstract: An asymmetric key cryptographic system is used to generate a cryptographic certificate for authenticating a memory module. This certificate is generated based on information, readable by the authenticator (e.g., host system), from at least one device on the memory module that is not read in order to obtain the certificate. For example, the certificate for authenticating a module may be stored in the nonvolatile memory of a serial presence detect device. The certificate itself, however, is based at least in part on information read from at least one other device on the memory module. Examples of this other device include a registering clock driver, DRAM device(s), and/or data buffer device(s). In an embodiment, the information read from a device (e.g., DRAM) may be based on one or more device fingerprint(s) derived from physical variations that occur naturally, and inevitably, during integrated circuit manufacturing.
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公开(公告)号:US20230305915A1
公开(公告)日:2023-09-28
申请号:US18092556
申请日:2023-01-03
Applicant: Rambus Inc.
Inventor: Thomas J. GIOVANNINI , Catherine CHEN , Scott C. BEST , John Eric LINSTADT , Frederick A. WARE
CPC classification number: G06F11/079 , G06F11/073 , G06F11/0772 , G06F13/00 , G11C5/04 , G11C7/20 , G11C8/12 , G11C29/26 , G11C29/44
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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公开(公告)号:US20210090614A1
公开(公告)日:2021-03-25
申请号:US17068505
申请日:2020-10-12
Applicant: Rambus Inc.
Inventor: Scott C. BEST , John W. POULTON
Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.
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公开(公告)号:US20180053544A1
公开(公告)日:2018-02-22
申请号:US15552569
申请日:2016-02-22
Applicant: RAMBUS INC.
Inventor: Frederick A. WARE , Ely K. TSERN , John Eric LINDSTADT , Thomas J. GIOVANNINI , Scott C. BEST , Kenneth L. WRIGHT
IPC: G11C11/4093 , H01L25/18 , G11C11/4096 , G11C11/4076 , H01L25/065 , G11C11/408
CPC classification number: G11C11/4093 , G11C5/025 , G11C5/063 , G11C7/10 , G11C7/1012 , G11C7/1066 , G11C7/1093 , G11C8/12 , G11C11/4076 , G11C11/408 , G11C11/4096 , G11C29/824 , H01L24/16 , H01L24/48 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/0401 , H01L2224/04042 , H01L2224/06135 , H01L2224/06136 , H01L2224/13025 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06562 , H01L2225/06572 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2224/13099 , H01L2224/45099
Abstract: A memory system includes dynamic random-access memory (DRAM) component that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.
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公开(公告)号:US20240320080A1
公开(公告)日:2024-09-26
申请号:US18586907
申请日:2024-02-26
Applicant: Rambus Inc.
Inventor: Thomas J. GIOVANNINI , Catherine CHEN , Scott C. BEST , John Eric LINSTADT , Frederick A. WARE
CPC classification number: G06F11/079 , G06F11/073 , G06F11/0772 , G06F13/00 , G11C5/04 , G11C7/20 , G11C8/12 , G11C29/26 , G11C29/44
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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公开(公告)号:US20240185894A1
公开(公告)日:2024-06-06
申请号:US18537347
申请日:2023-12-12
Applicant: Rambus Inc.
Inventor: Scott C. BEST , John W. POULTON
CPC classification number: G11C5/144 , G06F11/0727 , G06F11/076 , G06F11/0793 , G06F13/4072 , G11C5/145 , H04L1/203 , H04L25/0264 , H04L25/08
Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.
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公开(公告)号:US20220343953A1
公开(公告)日:2022-10-27
申请号:US17668606
申请日:2022-02-10
Applicant: Rambus Inc.
Inventor: Scott C. BEST , John W. POULTON
Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.
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公开(公告)号:US20210303383A1
公开(公告)日:2021-09-30
申请号:US17236445
申请日:2021-04-21
Applicant: Rambus Inc.
Inventor: Thomas J. GIOVANNINI , Catherine CHEN , Scott C. BEST , John Eric LINSTADT , Frederick A. WARE
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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公开(公告)号:US20200185009A1
公开(公告)日:2020-06-11
申请号:US16696780
申请日:2019-11-26
Applicant: Rambus Inc.
Inventor: Scott C. BEST , John W. POULTON
Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.
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