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    FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE
    4.
    发明申请
    FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE 有权
    半导体非易失性存储器件的制造方法和结构

    公开(公告)号：US20150221664A1

    公开(公告)日：2015-08-06

    申请号：US14685093

    申请日：2015-04-13

    Applicant: Renesas Electronics Corporation

    Inventor： Digh HISAMOTO ,  Shinichiro KIMURA ,  Kan YASUI ,  Nozomu MATSUZAKI

    IPC: H01L27/115

    CPC classification number: H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

    Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

    Abstract translation: 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210151609A1

    公开(公告)日：2021-05-20

    申请号：US17084163

    申请日：2020-10-29

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Digh HISAMOTO ,  Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

    IPC: H01L29/792 ,  H01L27/092 ,  H01L27/11568 ,  H01L29/78

    Abstract: A semiconductor device includes a memory cell which is configured of a FinFET having a split-gate type MONOS structure, the FinFET has a plurality of source regions formed in a plurality of fins, and the plurality of source regions are commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions are commonly connected by a bit line contact, and the FinFET constitutes a memory cell of 1 bit.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180082745A1

    公开(公告)日：2018-03-22

    申请号：US15640568

    申请日：2017-07-02

    Applicant: Renesas Electronics Corporation

    Inventor： Digh HISAMOTO

    IPC: G11C16/10 ,  G11C16/24 ,  G11C16/30

    CPC classification number: G11C16/10 ,  G11C8/08 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3418 ,  H01L29/785

    Abstract: Provided is a semiconductor device including nonvolatile memory cells each including a FinFET having excellent memory characteristics. The semiconductor device includes a semiconductor substrate, memory cells each formed in the semiconductor substrate and having a split-gate structure including an opposed-gate selection gate electrode, a memory gate electrode, and a pair of terminals, and a word line driver circuit which supplies a selection voltage to a selection gate electrode of the selected one of the memory cells and supplies a non-selection voltage to the selection gate electrode of the non-selected one of the memory cells. The word line driver circuit supplies, as the non-selection voltage, a voltage which is negative or positive relative to a potential in the semiconductor substrate so as to bring a selection transistor corresponding to the selection gate electrode of the non-selected memory cell into an OFF state.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
    半导体器件及制造半导体器件的方法

    公开(公告)号：US20170062440A1

    公开(公告)日：2017-03-02

    申请号：US15248159

    申请日：2016-08-26

    Applicant: Renesas Electronics Corporation

    Inventor： Tsuyoshi ARIGANE ,  Digh HISAMOTO

    IPC: H01L27/115 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L27/1157 ,  H01L21/32133 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/42368 ,  H01L29/66833 ,  H01L29/792

    Abstract: A property of a semiconductor device having a non-volatile memory is improved. A semiconductor device, which has a control gate electrode part and a memory gate electrode part placed above a semiconductor substrate of a non-volatile memory, is configured as follows. A thick film portion is formed in an end portion of the control gate insulating film on the memory gate electrode part side, below the control gate electrode part. According to this configuration, even when holes are efficiently injected to a corner portion of the memory gate electrode part by an FN tunnel erasing method, electrons can be efficiently injected to the corner portion of the memory gate electrode part by an SSI injection method. Thus, a mismatch of the electron/hole distribution can be moderated, so that the retention property of the memory cell can be improved.

    Abstract translation: 改善了具有非易失性存储器的半导体器件的特性。 具有设置在非易失性存储器的半导体衬底上方的控制栅电极部分和存储栅电极部分的半导体器件被配置如下。 在控制栅绝缘膜的存储栅电极部分侧的控制栅电极部分的下方形成厚膜部分。 根据该结构，即使通过FN隧道擦除法将存储器栅电极部的角部高效地注入孔，也可以通过SSI注入法将电子有效地注入到存储栅电极部的角部。 因此，可以缓和电子/空穴分布的不匹配，从而可以提高存储单元的保持性。

    NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING EMBEDDED NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH SIDEWALL GATE
    8.
    发明申请
    NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING EMBEDDED NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH SIDEWALL GATE 有权
    非挥发性半导体器件及其制造嵌入式非易失性半导体存储器件的方法

    公开(公告)号：US20130065368A1

    公开(公告)日：2013-03-14

    申请号：US13671482

    申请日：2012-11-07

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kan YASUI ,  Digh HISAMOTO ,  Tetsuya ISHIMARU ,  Shin-ichiro KIMURA

    IPC: H01L21/336

    CPC classification number: H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

    Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

    Abstract translation: 提供了一种制造非易失性半导体存储器件的方法，其克服了由于利用侧壁结构同时形成自对准分裂栅型存储单元而产生的最佳栅极高度的差异而引入的注入离子的问题，以及 一个缩放的MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210143260A1

    公开(公告)日：2021-05-13

    申请号：US17084097

    申请日：2020-10-29

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Digh HISAMOTO ,  Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

    IPC: H01L29/423 ,  H01L29/78 ,  H01L29/792 ,  H01L29/10 ,  H01L21/28

    Abstract: A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.

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